Output buffer circuit of semiconductor integrated circuit

Claim 2

An output buffer for producing an output data at an output terminal (26) comprising: a first MOS transistor (18) for charging said out­put terminal (26) toward a first supply potential when said first MOS transistor (18) turned on, said first MOS transistor (18) having a gate, a source and a drain, said source and drain connected between said output ter­minal (26) and a first supply potential terminal; a second MOS transistor (25) for discharging said output terminal (26) toward a second supply potential when said second MOS transistor (25) turned on, said second MOS transistor (25) having a gate, a source and a drain, said source and drain of said second MOS tran­sistor (25) connected between said output terminal (26) and a second supply potential terminal; and a resistance means (28) for charging said gate of said second MOS transistor (25) toward said first supply potential when turned on, said resistance means (28) connected between said first supply potential terminal and said gate of said second MOS transistor (25), said resistance means (28) having nearly a constant resist­ance value.

Claim 3

The output buffer according to claim 1, characterized in that said first MOS transistor (18) is a p-channel FET and said second MOS transistor (25) is an n-channel FET.

Claim 4

The output buffer according to claim 1, characterized in that said resistance means (28) includes a resistive element (28) composed of poly­silicon or an N⁺ or a P⁺ diffusion layer.

Claim 5

The output buffer according to claim 1, characterized in that said resistance means (28) includes a third MOS transistor (41).

Claim 6

The output buffer according to claim 1, characterized in that said resistance means (28) includes a plurality of MOS transistors (41′, 42) coupled in parallel with each other.

Claim 7

The output buffer according to claim 3, characterized in that said resistance means (28) further includes a fourth MOS transistor (23), connected between said resistive element (28) and said first supply poten­tial terminal, for charging said gate of said second MOS transistor (25) when turned on.

Claim 8

The output buffer according to claim 4, characterized in that said resistance means (28) further includes a fourth MOS transistor (23) connected between said third MOS transistor (41) and said first supply potential terminal, said gate of said second MOS tran­sistor (25) charged toward said first supply potential through said third and fourth MOS transistors (41, 23).

Claim 9

The output buffer according to claim 5, characterized in that said resistance means (28) further includes a fourth MOS transistor (23) connected between said plurality of MOS transistors (41′, 42) and said first supply potential terminal, said gate of said second MOS transistor (25) charged toward said first supply potential through said plurality of MOS tran­sistors (41′, 42) and said fourth MOS transistor (23).

Claim 10

The output buffer according to claim 6, characterized in that the resistance values of said resistive element (28) and said fourth MOS transistor (23) are nearly equal when they charge said gate of said second MOS transistor (25).

Claim 11

The output buffer according to claim 7, characterized in that the resistance values of said third MOS transistor (41) and said fourth MOS transistor (23) are nearly equal when they charge said gate of said second MOS transistor (25).

Claim 12

The output buffer according to claim 8, characterized in that the resistance values of said plu­rality of MOS transistors (41′, 42) and said fourth MOS transistor (23) are nearly equal when they charge said gate of said second MOS transistor (25).

Claim 13

An output buffer for producing an output data at an output terminal (26) comprising: a first MOS transistor (18) for charging said output terminal (26) toward a first supply potential when said first MOS transistor (18) turned on, said first MOS transistor (18) having a gate, a source and a drain, said source and drain connected between said output terminal (26) and a first supply potential ter­minal; a second MOS transistor (25) for discharging said output terminal (26) toward a second supply potential when said second MOS transistor (25) turned on, said second MOS transistor (25) having a gate, a source and a drain, said source and drain of said second MOS tran­sistor (25) connected between said output terminal (26) and a second supply potential terminal; a first resistance means (28) for charging said gate of said second MOS transistor (25) toward said first supply potential when turned on, said first resistance means (28) connected between said first supply potential terminal and said gate of said second MOS transistor (25), said first resistance means (28) having nearly a constant resistance value; a third MOS transistor (24) connected between said gate of said second MOS transistor (25) and said second supply potential terminal; a fourth MOS transistor (16) connected between said gate of said first MOS transistor (18) and said first supply potential terminal; and a fifth MOS transistor (17) connected between said gate of said first MOS transistor (18) and said second supply potential terminal.

Claim 14

An output buffer for producing an output data at an output terminal (26) comprising: a first MOS transistor (18) for charging said output terminal (26) toward a first supply potential when said first MOS transistor (18) turned on, said first MOS transistor (18) having a gate, a source and a drain, said source and drain connected between said output terminal (26) and a first supply potential ter­minal; a second MOS transistor (25) for discharging said output terminal (26) toward a second supply potential when said second MOS transistor (25) turned on, said second MOS transistor (25) having a gate, a source and a drain, said source and drain of said second MOS tran­sistor (25) connected between said output terminal (26) and a second supply potential terminal; a first resistance means (28) for charging said gate of said second MOS transistor (25) toward said first supply potential when turned on, said first resistance means (28) connected between said first supply potential terminal and said gate of said second MOS transistor (25), said first resistance means (28) having nearly a constant resistance value; a third MOS transistor (24) connected between said gate of said second MOS transistor (25) and said second supply potential terminal; a fourth MOS transistor (16) connected between said gate of said first MOS transistor (18) and said first supply potential terminal; and a fifth MOS transistor (17) connected between said gate of said first MOS transistor (18) and said second supply potential terminal.

Claim 15

The output buffer according to claim 12, characterized in that said first MOS transistor (18) is a p-channel FET and said second MOS transistor (25) is an n-channel FET.

Claim 16

The output buffer according to claim 12, characterized in that said first resistance means (28) includes a resistive element (28) composed of poly­silicon or an N⁺ or a P⁺ diffusion layer.

Claim 17

The output buffer according to claim 12, characterized in that said first resistance means (28) includes a sixth MOS transistor (41).

Claim 18

The output buffer according to claim 12, characterized in that said first resistance means (28) includes a plurality of MOS transistors (41′, 42) coupled in parallel with each other.

Claim 19

The output buffer according to claim 12, characterized by further comprising a second resistance means (29) connected between said gate of said first MOS transistor (18) and said fifth MOS transistor (17).

Claim 20

The output buffer according to claim 7, characterized in that said third MOS transistor (41) is controlled by a first logic level signal, and said fourth MOS transistor (23) is controlled by a second logic level signal.

Claim 21

The output buffer according to claim 15, characterized in that said first resistance means (28) further includes a seventh MOS transistor (23) connected between said sixth MOS transistor (41) and said first supply potential terminal, said gate of said second MOS transistor (25) charged toward said first supply poten­tial through said sixth and seventh MOS transistors (41, 23).

Claim 22

The output buffer according to claim 19, characterized in that said sixth MOS transistor (41) is controlled by a first logic level signal, said seventh MOS transistor (23) is controlled by a second logic level signal, and the resistance values of said sixth and seventh MOS transistors (41, 23) are nearly equal when said gate of second MOS transistors (25) is charged.