Patent EP0350219A2 successfully refreshed from Google Patents.
EP0350219A2
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EP
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CMOS latch circuit
Assignee: NCR Voyix Corp
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Filing: 1989-06-30
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Granted: —
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Expires: 2009-06-30
Abstract
Abstract A no-leak CMOS latch circuit (10) has a data input line (12) for supplying a low or high data signal, a single clock input line (14), a data storage node (16), a complementary data output node (18), and first and second power supply terminals. The latch (10) has an NMOS input transistor (24) for supplying either a low or degraded high data signal to the data storage node (16). A CMOS inverter (26) connects the data storage node (16) to the complementary data output node (18). A dynamic inverter (32) including three series-connected transistors (34,36,38) responds to the signals on the clock input line (14) and output node (18) to connect either the first or second power supply terminals to the data storage node (18). In this manner the data storage node (16) is maintained at a level that prevents static power dissipation from the CMOS inverter (26).
Inventors
- 👤 Mukesh Bhogilal Suthar
- 👤 Ikuo Jimmy Sanwo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:01
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
192 words
A CMOS latch circuit having a data input line (12) adapted to supply a high or a low data signal, a single clock input line (14), a data storage node (16), a complementary data output node (18), first and second power supply terminals (20a,20b;22a,22b), input means responsive to a signal from said clock input line (14), to supply a low or degraded high signal from a data input line (12) to said data storage node (16), and a CMOS inverter including first and second series connected transistors (25,30), said inverter being connected between said storage node (16), and said complementary data output node (18), characterized by series connected third, fourth and fifth transistors (34,36,38), said third and fifth transistors having their gates connected to said complementary data output node (18), and said fourth transistor having its gate connected to said clock input line (14), in that said third transistor (34) has its source-driven path connected between said first power supply terminal (20b) and said data storage node (16) and in that said fourth and fifth transistors (36,38) are series-connected between said data storage node (16) and said second power supply terminal (22b)
Claim 2
Dependent Claim
192 words
A CMOS latch circuit having a data input line (12) adapted to supply a high or a low data signal, a single clock input line (14), a data storage node (16), a complementary data output node (18), first and second power supply terminals (20a,20b;22a,22b), input means responsive to a signal from said clock input line (14), to supply a low or degraded high signal from a data input line (12) to said data storage node (16), and a CMOS inverter including first and second series connected transistors (25,30), said inverter being connected between said storage node (16), and said complementary data output node (18), characterized by series connected third, fourth and fifth transistors (34,36,38), said third and fifth transistors having their gates connected to said complementary data output node (18), and said fourth transistor having its gate connected to said clock input line (14), in that said third transistor (34) has its source-driven path connected between said first power supply terminal (20b) and said data storage node (16) and in that said fourth and fifth transistors (36,38) are series-connected between said data storage node (16) and said second power supply terminal (22b)
Claim 3
Dependent Claim
69 words
A CMOS latch circuit according to claim 1, characterized in that said first transistor (28) is a PMOS transistor, said second transistor (30) is an NMOS transistor, the drains of said first and second transistors (28,30) are connected to said complementary data output node (18), the gates are connected to said data storage node (16) and the sources are connected to said first and second power supplies (20a,22a) respectively.
Claim 4
Dependent Claim
29 words
A CMOS latch circuit according to claim 2, characterized in that said third and fourth transistors (34,36) are PMOS transistors and said fifth transistor (38) is an NMOS transistor.
Claim 5
Dependent Claim
25 words
A CMOS latch circuit according to any one of the preceding claims, characterized in that said third transistor (34) has a relatively small width-to-length ratio.
Claim 6
Dependent Claim
50 words
A CMOS latch circuit according to any one of the preceding claims, characterized in that said input means includes a sixth transistor (24) having its gate connected to said clock input line (14) and its source-drain path connected between said data input line (12) and said data storage node (16).
Claim 7
Dependent Claim
18 words
A CMOS circuit according to claim 5, characterized in that said sixth transistor is an NMOS transistor (24).
Claim 8
Dependent Claim
27 words
A CMOS circuit according to any one of the preceding claims, characterized in that said data input line (12) receives its input from an N channel multiplexer.
References Cited (Backward Citations)
No citation records indexed.
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