Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
123 words
A sample-hold circuit comprising a large number of sample-hold elements (2Am, ..., 2Am+5), and a multi-stage shift register (7A) for controlling sampling timings of said sample-hold elements, including a large number of stages corresponding to said respective sample-hold elements, characterized in that each stages (20, 20m, ..., 20m+5) of said multi-stage shift register includes an input gate (21, 21m, ..., 21m+5) for taking a signal shifted from the preceding stage thereinto, an output gate (22, 22m, ..., 22m+5) for shifting the signal taken in by said input gate to the succeeding stage, respective sampling timings of said sample-hold elements corresponding to respective stages being determined by signals taken in between said input and output gates through said input gates at said respective stages.
Claim 2
Dependent Claim
123 words
A sample-hold circuit comprising a large number of sample-hold elements (2Am, ..., 2Am+5), and a multi-stage shift register (7A) for controlling sampling timings of said sample-hold elements, including a large number of stages corresponding to said respective sample-hold elements, characterized in that each stages (20, 20m, ..., 20m+5) of said multi-stage shift register includes an input gate (21, 21m, ..., 21m+5) for taking a signal shifted from the preceding stage thereinto, an output gate (22, 22m, ..., 22m+5) for shifting the signal taken in by said input gate to the succeeding stage, respective sampling timings of said sample-hold elements corresponding to respective stages being determined by signals taken in between said input and output gates through said input gates at said respective stages.
Claim 3
Dependent Claim
47 words
A sample-hold circuit as set forth in claim 1, wherein said input gates (21, 21m, ..., 21m+5) of respective stages and said output gates (22, 22m, ..., 22m+5) of respective stages of said multi-stage shift register are driven by control signals having phases opposite to each other.
Claim 4
Dependent Claim
124 words
A sample-hold circuit as set forth in claim 1, wherein each of said stages (20, 20m, ..., 20m+5) of said multi-stage shift register includes an input gate (21, 21m, ..., 21m+5) comprised of a first clocked inverter driven by a first clock (ø A ), an output gate (22, 22m, ..., 22m+5) comprised of a second clocked inverter driven by a second clock ( ø A ) having a phase opposite to that of said first clock, and an external output line (23, 23m, ..., 23m+5) connected to a connection wiring between said input gate and said output gate, respective sampling timings of said sample-hold elements corresponding to respective stages being determined by signals output from the external output lines of said respective stages.
Claim 5
Dependent Claim
35 words
A sample-hold circuit as set forth in claim 1, wherein said multi-stage shift register is of a structure folded at a wiring portion between a predetermined stage (20m+2) thereof and a stage (20m+3) succeeding thereto.