Differential analog comparator

Claim 2

An analog comparator formed on an integrated circuit for comparing a first voltage input to a second voltage input, CHARACTERIZED BY : a first string (21) of at least one cascaded gain stage (22), each stage having an input, an output and first and second power terminals, the corresponding power terminals coupling to first and second buses, the input of the first of the cascaded gain stages coupling to the first voltage input of the comparator; a second string (21′) of at least one cascaded gain stage, each stage having an input, an output and first and second power terminals, the corresponding power terminals coupling to the first and second buses, the input of the first of the cascaded gain stages coupling to the second voltage input of the comparator; a first current source (40) coupling to the first bus (32); and, a second current source (50) coupling to the second bus (33) and providing substantially the same current as the first current source.

Claim 3

The analog comparator recited in claim 1, further characterized by: at least one digital inverter (45) responsive to at least one of the outputs of the first and second strings of cascaded gain stages.

Claim 4

The analog comparator recited in claim 2, wherein each of the cascaded gain stage comprises a first transistor (30) of a first polarity and a second transistor (31) of a second polarity, each transistor having two output terminals and an input terminal, the input terminals of the two transistors coupling together to form the input to the gain stage, two corresponding output terminals from the two transistors coupling together to form the output of the gain stage, and the remaining output terminals of the two transistors forming the corresponding first and second power terminals of the gain stage.

Claim 5

An analog comparator formed in an integrated circuit for comparing a first voltage input to a second voltage input CHARACTERIZED BY : a first string (21) of at least one cascaded gain stage (22), each stage having an input, an output and first and second power terminals, the corresponding power terminals coupling to first and second buses, the input of the first of the cascaded gain stages coupling to the first voltage input of the comparator; a second string (21′) of at least one cascaded gain stage, each stage having an input, an output and first and second power terminals, the corresponding power terminals coupling to the first and second buses, the input of the first of the cascaded gain stages coupling to the second voltage input of the comparator; a current source (40) having a first and second outputs, the first output coupling to the first bus (32); a first current mirror (50) having a first control current input, a first control current output, a mirrored current input and a mirrored current output, the first control current input coupling to the second output of the current source and the mirrored current input coupling to the second bus (33); a first node (68) having a first predetermined voltage thereon; a first transistor network (61, 62) having first and second output terminals and an input terminal, the first output terminal coupling to the first control current output of the first current mirror, the second output terminal coupling to a first power source and the input terminal coupling to the first node; a second transistor network (65, 66) having two output terminals and two input terminals, the corresponding output terminals coupling between the mirrored current output of the first current mirror and the first power source, each input terminal coupling to the corresponding output of the first and second string of cascaded gain stages; and, such that the average of the voltages on the outputs of the first and second strings of cascaded gain stages is approximately that of the first predetermined voltage on the first node.

Claim 6

An analog comparator formed in an integrated circuit for comparing a first voltage input to a second voltage input CHARACTERIZED BY : a first string (21) of at least one cascaded gain stage (22), each stage having an input, an output and first and second power terminals, the corresponding power terminals coupling to first and second buses, the input of the first of the cascaded gain stages coupling to the first voltage input of the comparator; a second string (21′) of at least one cascaded gain stage, each stage having an input, an output and first and second power terminals, the corresponding power terminals coupling to the first and second buses, the input of the first of the cascaded gain stages coupling to the second voltage input of the comparator; a current source (40) having a first and second outputs, the first output coupling to the first bus (32); a first current mirror (50) having a first control current input, a first control current output, a mirrored current input and a mirrored current output, the first control current input coupling to the second output of the current source and the mirrored current input coupling to the second bus (33); a first node (68) having a first predetermined voltage thereon; a first transistor network (61, 62) having first and second output terminals and an input terminal, the first output terminal coupling to the first control current output of the first current mirror, the second output terminal coupling to a first power source and the input terminal coupling to the first node; a second transistor network (65, 66) having two output terminals and two input terminals, the corresponding output terminals coupling between the mirrored current output of the first current mirror and the first power source, each input terminal coupling to the corresponding output of the first and second string of cascaded gain stages; and, such that the average of the voltages on the outputs of the first and second strings of cascaded gain stages is approximately that of the first predetermined voltage on the first node.

Claim 7

The analog comparator recited in claim 4, wherein the first and second transistor networks operate as variable resistors responsive to voltages applied to the corresponding input terminals.

Claim 8

The analog comparator recited in claim 5, the current source further characterized by a second current mirror having a first, second and a third mirrored current outputs and a control current output, the control current output coupling to a predetermined current source, the first mirrored current output coupling to the first output of the current source and the second mirrored current output coupling to the second output of the current source; the first transistor network having a third output terminal; and the first current mirror being a compound current mirror having a second control current input and a second control current output, the second control current input coupling to the third mirrored current output of the second current mirror and the second control current output coupling to the third output terminal of the first transistor network.

Claim 9

The analog comparator recited in claim 6, further characterized by a third transistor network (76, 77), disposed between the second and third mirrored current outputs of the second current mirror and the first and second control current inputs of the first current mirror, responsive to a second predetermined voltage source (78).

Claim 12

The method for comparing first and second voltages of claim 8, wherein at least one of the current sources includes a current mirror, the current mirror being responsive to the remaining current source and is adapted to vary the magnification factor of the current mirror, further comprising the steps of: increasing the magnification factor of the current mirror in response to a first predetermined voltage source; sensing the average voltage of the amplified first and second voltages; and, decreasing the magnification factor of the current mirror in response to the sensed average voltage; such that the magnification factor settles to a value necessary for the average voltage of the amplified first and second voltages to be substantially the same as the first predetermined voltage.

Claim 13

The method for comparing first and second voltages of claim 9, further comprising the steps of: buffering at least one of the amplified first and second voltages with a first digital inverter having a predetermined threshold voltage; generating the first predetermined voltage from a second digital inverter having substantially the same threshold voltage as the first digital inverter by coupling the input of the second digital inverter to the output thereof.