Patent EP0349007A2 successfully refreshed from Google Patents.
EP0349007A2
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EP
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Semiconductor integrated circuit for neural network
Assignee: Hitachi Ltd
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Filing: 1989-06-30
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Granted: —
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Expires: 2009-06-30
Abstract
Abstract A semiconductor integrated circuit for constructing a neural network model comprises a differential amplifier (11) including one output terminal and two input terminals, an excitatory synapse circuit (2-2) connected to the non-inverting input terminal of said differential amplifier (11), and an inhibitory synapse circuit (2-1) connected to the inverting input terminal of said differential amplifier (11). Each of said excitatory and inhibitory synapse circuits (2-1, 2-2) includes a plurality of current switches, regulated current source circuits which are equal in number to said current switches and which determine currents to flow through said currents to flow through said current switches, and one load resistor which is connected to all of said current switches. Input terminals (P i ) of each said synapse circuit (2-1, 2-2) are designed to turn "on" and "off" the respective current switches and are connected to which external inputs or outputs of another neural circuit. Each regulated current source circuit is constructed of a circuit whose current value can be increased or decreased by a voltage externally applied separately, the value of the voltage for increasing or decreasing the current value corresponding to a synaptic weight.
Inventors
- 👤 Yoshito Nejime
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 15:07
CPC Classifications
G; G06; G06N; G06N3/00; G06N3/02; G06N3/06; G06N3/063; G06N3/065
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
196 words
A semiconductor integrated circuit for constructing a neural network model, characterized by a differential amplifier (11) having an output terminal and two differential input terminals, an excitatory synapse circuit (2-2) connected to the non-inverting input terminal of said differential amplifier (11), and an inhibitory synapse circuit (2-1) connected to the inverting input terminal of said differential amplifier (11), wherein each of said excitatory and inhibitory synapse circuits includes a plurality of current switches (Q i1 , Q i2 ), a regulated current source array (3) configured of regulated current source circuits (Q si ,r) being equal in number of said current switches (Q i1 ,Q i2 ) and determining values of currents to flow through said current switches, and one load resistor (R) connected to all of said current switches, input terminals (P i ) of each said synapse circuit (2) being constructed of terminals which turn "on" and "off" the respective current switches (Q i1 , Q i2 ) and to which external inputs or outputs of another circuit are connected, said regulated current source circuits (Q si ,r) having current values which can be respectively altered by voltages externally applied independently of one another.
Claim 2
Dependent Claim
196 words
A semiconductor integrated circuit for constructing a neural network model, characterized by a differential amplifier (11) having an output terminal and two differential input terminals, an excitatory synapse circuit (2-2) connected to the non-inverting input terminal of said differential amplifier (11), and an inhibitory synapse circuit (2-1) connected to the inverting input terminal of said differential amplifier (11), wherein each of said excitatory and inhibitory synapse circuits includes a plurality of current switches (Q i1 , Q i2 ), a regulated current source array (3) configured of regulated current source circuits (Q si ,r) being equal in number of said current switches (Q i1 ,Q i2 ) and determining values of currents to flow through said current switches, and one load resistor (R) connected to all of said current switches, input terminals (P i ) of each said synapse circuit (2) being constructed of terminals which turn "on" and "off" the respective current switches (Q i1 , Q i2 ) and to which external inputs or outputs of another circuit are connected, said regulated current source circuits (Q si ,r) having current values which can be respectively altered by voltages externally applied independently of one another.
Claim 3
Dependent Claim
55 words
The circuit of claim 1, wherein each said regulated current source circuit includes a MOS transistor (Q si ) with a floating gate and a resistor (r), a pulse voltage being impressed on said floating gate of said MOS transistor to control the value of current which said regulated current source circuit causes to flow.
Claim 4
Dependent Claim
50 words
The circuit of claim 1 or 2, wherein in said regulated current source array (3), a summation current with all of said regulated current source circuits (Q si ) included therein cause to flow is held constant by a single regulated current source (V EE ) which is separately provided.
Claim 5
Dependent Claim
42 words
The circuit of any one of Claims 1 to 3, wherein said regulated current source array (3) includes a plurality of transistors (Q si ) whose emitter areas differ in accordance with the values of currents to be respectively caused to flow.
Claim 6
Dependent Claim
68 words
The circuit of any one of claims 1 to 4, wherein each said current switch includes one pair of transistors (Q i1 , Q i2 ) and resistors (r d ) which are connected in series with emitters of the respective transistors, and said resistors are constructed of resistors, such as pinch resistors, whose resistances can be altered by an external voltage (V d ) or the like.
Claim 7
Dependent Claim
66 words
A semiconductor integrated circuit for constructing a neural network model, characterized in that said circuit comprises one output end and a plurality of input ends, and that an output which is developed from said output end is not endowed with a saturation characteristic, whereas sides of said plurality of input ends which receive external inputs or outputs of another circuit are respectively endowed with saturation characteristics.
Claim 8
Dependent Claim
66 words
A semiconductor integrated circuit for constructing a neural network model, characterized in that said circuit comprises one output end and a plurality of input ends, and that an output which is developed from said output end is not endowed with a saturation characteristic, whereas sides of said plurality of input ends which receive external inputs or outputs of another circuit are respectively endowed with saturation characteristics.
Claim 9
Dependent Claim
130 words
A semiconductor integrated circuit for a neural network model, characterized by a current comparison circuit (11) including an output terminal and two input terminals, an excitatory synapse circuit (2-2) connected in series with a non-inverting input terminal of said current comparison circuit (11) and having at least one current output type D/A converter, and an inhibitory synapse circuit (2-1) connected in series with an inverting input terminal of said current comparison circuit (11) and having at least one current output type D/A converter, wherein each of said excitatory and inhibitory synapse circuits (2-1, 2-2) includes a plurality of input terminals (P i ) which have weights, respectively, and to which external inputs or outputs of another neural circuit are connected in any desired combination of said plurality of input terminals.
Claim 10
Dependent Claim
130 words
A semiconductor integrated circuit for a neural network model, characterized by a current comparison circuit (11) including an output terminal and two input terminals, an excitatory synapse circuit (2-2) connected in series with a non-inverting input terminal of said current comparison circuit (11) and having at least one current output type D/A converter, and an inhibitory synapse circuit (2-1) connected in series with an inverting input terminal of said current comparison circuit (11) and having at least one current output type D/A converter, wherein each of said excitatory and inhibitory synapse circuits (2-1, 2-2) includes a plurality of input terminals (P i ) which have weights, respectively, and to which external inputs or outputs of another neural circuit are connected in any desired combination of said plurality of input terminals.
Claim 11
Dependent Claim
43 words
The circuit of claim 7, wherein each said synapse circuit (2-1, 2-2) includes the D/A converter in which resistors of resistances R and 2R and a current switch circuit formed of P-N-P transistors constitute one set, a plurality of such sets being connected.
References Cited (Backward Citations)
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