Patent EP0348113A2 successfully refreshed from Google Patents.
EP0348113A2
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EP
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Programmable burst apparatus and technique
Assignee: Advanced Micro Devices Inc
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Filing: 1989-06-16
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Granted: —
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Expires: 2009-06-16
Abstract
Abstract A data processing system having a processor capable of initiating a request for a burst of data transfer and a memory. A memory controller is connected to the processor and to the memory. The controller includes a burst count register having a value stored therein representative of the maximum number of data transfers allowed per burst. Also in the memory controller is a column latch/counter having stored therein a value representative of a column latch address. The column latch/counter is capable of incrementing the address. Finally, included in the memory controller is a programmable mask for specifying bits in the column latch/counter to be compared to corresponding bits in the burst count register.
Inventors
- 👤 Percy P. Aria
- 👤 David W. Stoenner
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 14:25
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F12/00; G06F12/02; G06F12/0215; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0879
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
106 words
In a data processing system comprising a processor capable of initiating a request for a burst of data transfer and a memory, the improvement comprising a memory controller operatively connected to said processor and to said memory, said controller comprising: a) a burst count register having stored therein a value representative of the maximum number of data transfers allowed per burst; b) a column latch/counter having stored therein the value representative of a column latch address and being capable of incrementing said address; and c) a programmable mask for specifying bits in said column latch/counter to be compared to corresponding bits in said burst count register.
Claim 2
Dependent Claim
106 words
In a data processing system comprising a processor capable of initiating a request for a burst of data transfer and a memory, the improvement comprising a memory controller operatively connected to said processor and to said memory, said controller comprising: a) a burst count register having stored therein a value representative of the maximum number of data transfers allowed per burst; b) a column latch/counter having stored therein the value representative of a column latch address and being capable of incrementing said address; and c) a programmable mask for specifying bits in said column latch/counter to be compared to corresponding bits in said burst count register.
Claim 3
Dependent Claim
18 words
The data processing system in accordance with claim 1 wherein said memory comprises a dynamic random access memory.
Claim 4
Dependent Claim
29 words
The data processing system in accordance with claim 1 wherein said processor is incapable of monitoring the number of data transfers that occur within a burst of data transfers.
Claim 5
Dependent Claim
30 words
The data processing system in accordance with claim 3 wherein said column latch/counter is initially loaded with a starting address for the burst of data transfers specified by said processor.
Claim 6
Dependent Claim
42 words
The data processing system in accordance with claim 3 wherein a data transfer of less than a whole predetermined burst length is performed by said controller and all consecutive bursts thereafter are aligned so that only full burst lengths are subsequently transferred.
Claim 7
Dependent Claim
39 words
The data processing system in accordance with claim 1 wherein said bits in said column latch/counter are compared to said corresponding bits in said burst count register by means of comparator logic means operatively connected to said programmable mask.
Claim 8
Dependent Claim
31 words
The data processing system in accordance with claim 6 wherein said comparison of said burst count register bits with said column latch/counter bits is performed on a bit by bit basis.
Claim 9
Dependent Claim
18 words
The data processing system in accordance with claim 1 wherein said programmable mask is programmed by said processor.
Claim 10
Dependent Claim
148 words
A technique for aligning consecutive burst accesses in a data processing system having a processor and a memory, the steps comprising: a) loading a burst count register with a value representative of the maximum number of data transfers permitted in a data transfer burst; b) loading a loadable counter with a value representative of a memory address to be accessed; c) comparing the bits in said burst count register with the corresponding bits in said counter on a bit by bit basis to generate intermediate comparison signals, one signal for each set of compared bits; d) masking said intermediate comparison signals on a bit by bit basis with a mask value to generate masked output values; and e) ANDing all of said masked output values to generate a comparator output signal, said comparator output signal indicative of an end of burst when said comparator output signal is high.
Claim 11
Dependent Claim
148 words
A technique for aligning consecutive burst accesses in a data processing system having a processor and a memory, the steps comprising: a) loading a burst count register with a value representative of the maximum number of data transfers permitted in a data transfer burst; b) loading a loadable counter with a value representative of a memory address to be accessed; c) comparing the bits in said burst count register with the corresponding bits in said counter on a bit by bit basis to generate intermediate comparison signals, one signal for each set of compared bits; d) masking said intermediate comparison signals on a bit by bit basis with a mask value to generate masked output values; and e) ANDing all of said masked output values to generate a comparator output signal, said comparator output signal indicative of an end of burst when said comparator output signal is high.
References Cited (Backward Citations)
No citation records indexed.
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