Static random access memory device with a power dissipation reduction function

Claim 2

A static random access memory device having a memory cell array having a plurality of static memory cells (MC1 to MCn), a pair of bit lines (BL1, BL1 ) for transferring data to and from said memory cells in said memory cell array (BL1, BL1 ), and a write circuit (17) for supplying write data to said bit line pair, said static random access memory device characterized by memory cell drive means (13) for selectively driving one of said memory cells in accordance with a row address signal supplied from exterior; write mode detecting means (31) for detecting a signal state transition of a write enable signal changing to an active state; input data transition detecting means (32) for detecting a transition of the input data supplied from exterior, during a continuation of the active state of said write enable signal; address signal transition detecting means (33) for detecting a transition of an externally applied address signal during an active state of said write enable signal; pulse signal generating means (34) for generating a pulse signal with a predetermined pulse width in response to any of the detecting signals outputted from said write mode detecting means (31), said input data transition detecting means (32), and said address signal transition detecting means (33); drive control means (G1) for permitting said memory cell drive means (13) to operate during a period that said pulse signal generating means (34) generates a pulse signal, and for inhibiting said memory cell drive means (13) from operating during a period that said pulse signal generating means rests; and write circuit control means (35, 19) for supplying write data based on said input data to said write circuit (17) during a period that said pulse signal generating means (34) generates a pulse signal, and for supplying to said write circuit initial data to set said bit line pair (BL1, BL1 bar) at the same potentials during said period that said pulse signal generating means (34) rests.

Claim 3

A static random access memory device according to claim 1, characterized in that said pulse signal generating means (34) simultaneously generates a first pulse signal and a second pulse signal of a wider pulse width than that of said first pulse signal, said first pulse signal being supplied to said drive control means (G1), and said second pulse signal being supplied to said write circuit control means (35, 19).

Claim 4

A static random access memory device according to claim 1, characterized in that said write circuit (17) includes write buffers (101, 102) for supplying write data to said bit line pair (BL1, BL1 ) and a switch circuit (Q3, Q4) inserted between said paired bit lines and the write buffers (101, 102), and said switch cir­cuit (Q3, Q4) is turned on only under conditions that said write enable signal is in an active state and said pulse generating means (34) is generating a pulse signal.

Claim 5

A static random access memory device according to claim 1, characterized in that said memory cell drive means (13) includes a row decoder.

Claim 6

A static random access memory device according to claim 4, characterized in that said drive control means (G1) includes a gate circuit gated by the pulse signal outputted from said pulse signal generating means (34), said gate circuit being provided on the output side of said row decoder.

Claim 7

A static random access memory device according to claim 1, characterized by further comprising a load circuit connected at one end to said paired bit lines (BL1, BL1 ) and at the other end to a power source poten­tial supply terminal in a first logic level 1, and characterized in that said write circuit control means (35, 19) supplies write data based on said input data to said write circuit (17) so that during said period that said pulse signal generating means (34) generates a pulse signal, one of said paired bit lines (BL1, BL1 ) is set in the first logic level, while the other in a second logic level, and said write circuit control means (34, 19) supplies to said write circuit (17) write data to set both of said paired bit lines (BL1, BL1 ) in said first logic level during said period that said pulse signal generating means (34) rests.

Claim 8

A static random access memory device having a memory cell array having a plurality of static memory cells (MC1 to MCn), a pair of bit lines (BL1, BL1 ) for transferring data to and from said memory cells in said memory cell array (BL1, BL1 ), memory cell drive means (13) for selectively driving one of said memory cells in accordance with a row address signal supplied from exterior, said static random access memory device characterized by memory cell drive means (13) for selectively one of said memory cells in accordance with a row address signal externally supplied; write mode detecting means (31) for detecting a signal state transition of a write enable signal changing to an active state; input data transition detecting means (32) for detecting a transition of the input data supplied from exterior, during a continuation of the active state of said write enable signal; address signal transition detecting means (33) for detecting a transition of an externally applied address signal during an active state of said write enable signal; pulse signal generating means (34) for simulta­neously generating a first pulse signal and a second pulse signal of a wider pulse width than that of said first pulse signal in response to any of the detecting signals outputted from said write mode detecting means (31), said input data transition detecting means (32), and an address signal transition detecting means (34); a write circuit (17) for supplying write data to said paired bit lines (BL1, BL1 ) including write buffers (101, 102) for supplying write data to said bit line pair (BL1, BL1 ) and a switch circuit (Q3, Q4) inserted between said paired bit lines and the write buffers (101, 102), and said switch circuit (Q3, Q4) is turned on only under conditions that said write enable signal is in an active state and said pulse generating means (34) is generating a pulse signal; drive control means (G1) for permitting said memory cell drive means (13) to operate during a period that said pulse signal generating means (34) generates said first pulse signal, and for inhibiting said memory cell drive means (13) from operating during a period that said pulse signal generating means rests; and write circuit control means (35, 19) for supplying write data based on said input data to said write cir­cuit (17) during said period that said pulse signal generating means (34) generates said second pulse signal, and for supplying to said write circuit initial data to set said bit line pair (BL1, BL1 ) at the same potentials during said period that said pulse signal generating means (34) rests.

Claim 9

A static random access memory device having a memory cell array having a plurality of static memory cells (MC1 to MCn), a pair of bit lines (BL1, BL1 ) for transferring data to and from said memory cells in said memory cell array (BL1, BL1 ), memory cell drive means (13) for selectively driving one of said memory cells in accordance with a row address signal supplied from exterior, said static random access memory device characterized by memory cell drive means (13) for selectively one of said memory cells in accordance with a row address signal externally supplied; write mode detecting means (31) for detecting a signal state transition of a write enable signal changing to an active state; input data transition detecting means (32) for detecting a transition of the input data supplied from exterior, during a continuation of the active state of said write enable signal; address signal transition detecting means (33) for detecting a transition of an externally applied address signal during an active state of said write enable signal; pulse signal generating means (34) for simulta­neously generating a first pulse signal and a second pulse signal of a wider pulse width than that of said first pulse signal in response to any of the detecting signals outputted from said write mode detecting means (31), said input data transition detecting means (32), and an address signal transition detecting means (34); a write circuit (17) for supplying write data to said paired bit lines (BL1, BL1 ) including write buffers (101, 102) for supplying write data to said bit line pair (BL1, BL1 ) and a switch circuit (Q3, Q4) inserted between said paired bit lines and the write buffers (101, 102), and said switch circuit (Q3, Q4) is turned on only under conditions that said write enable signal is in an active state and said pulse generating means (34) is generating a pulse signal; drive control means (G1) for permitting said memory cell drive means (13) to operate during a period that said pulse signal generating means (34) generates said first pulse signal, and for inhibiting said memory cell drive means (13) from operating during a period that said pulse signal generating means rests; and write circuit control means (35, 19) for supplying write data based on said input data to said write cir­cuit (17) during said period that said pulse signal generating means (34) generates said second pulse signal, and for supplying to said write circuit initial data to set said bit line pair (BL1, BL1 ) at the same potentials during said period that said pulse signal generating means (34) rests.

Claim 10

A static random access memory device according to claim 7, characterized in that said memory cell drive means (13) includes a row decoder.

Claim 11

A static random access memory device according to claim 8, characterized in that said drive control means (G1) includes a gate circuit gated by the pulse signal outputted from said pulse signal generating means (34), said gate circuit being provided on the output side of said row decoder.

Claim 12

A static random access memory device according to claim 7, characterized by further comprising a load circuit connected at one end to said paired bit lines (BL1, BL1 ) and at the other end to a power source poten­tial supply terminal in a first logic level, and charac­terized in that said write circuit control means (35, 19) supplies write data based on said input data to said write circuit (17) so that during said period that said pulse signal generating means (34) generates the second pulse signal, one of said paired bit lines (BL1, BL1 ) is set in the first logic level, while the other in a second logic level, and said write circuit control means (34, 19) supplies to said write circuit (17) write data to set both of said paired bit lines (BL1, BL1 ) in said first logic level during said period that said pulse signal generating means (34) rests.