Binary carry or borrow look-ahead circuit

Claim 2

A binary operator, having a carry propagate signal and carry generate signal generating means (100) which receives two pieces of n-bit binary data (A. B) and generates a carry propagate signal (P ; ) and a carry generate signal (G ; ) of various digits, said two pieces of n-bit binary data (A, B) are divided into blocks of predetermined number of bits, each data of said divided blocks is processed in parallel by a plurality of block adders based on the corresponding carry propagate signal (P;) and carry generate signal (G ; ), and a real sum signal (F ; ) is output by calculating the arithmetic sum of said two n-bit binary data (A, B), wherein said binary operator comprises: a cumulative carry propagate signal generating means (106), connected to said carry propagate signal and carry generate signal generating means (100) and receiving carry propagate signals (P M P i-1 ) of the various digits in said block adders, for generating a cumulative carry propagate signal (BP i-1 *) by calculating said carry propagate signals (P M ~ p i-1 ); a cumulative carry generate signal generating means (107), connected to said carry propagate signal and carry generate signal generating means (100) and receiving the carry propagate signals (P M ~P i-1 ) and carry generate signals (G M ~G i-1 ) of the various digits in said block adders, for generating a cumulative carry generate signal (BG i-1 *) by calculating said carry propagate signals (P M ~P i-1 ) and said carry generate signals(G M ~G i-1 ); a real sum signal generating means (108), connected to said carry propagate signal and carry generate signal generating means(100), said cumulative carry propagate signal generating means (106) and said cumulative carry generate signal generating means (107) and receiving the carry propagate signal (P ; ) of various digits, the cunulative carry propagate signal (BP i-1 *) from said cumulative carry propagate signal generating means (106), the cumulative carry generate signal (BG i-1 *) from said cumulative carry generate signal generating means(107) and a real carry signal (C M-1 ), for generating the real sum signal (F ; ) by calculating said carry propagate signal (P,), said cumulative carry propagate signal (BP i-1 *), said cumulative carry generated signal (BG i-1 *) and said real carry signal (C M-1 ).

Claim 3

A binary operator according to claim 1, wherein an i-th digit of said real sum signal generating means (108) generates the real sum signal (F ; ) of said i-th digit by calculating the carry propagate signal (P ; ) of said i-th digit, the cumulative carry propagate signal (BP i-1 *) of said (i-1)-th digit, the cumulative carry generate signal (BG i-1 *) of said (i-1)-th digit and a real carry signal (C M . i ) advanced from the lower digit to the block adder to which it belongs.

Claim 4

A binary operator according to claim 1, wherein said binary operator comprises a plurality of carry select adder circuits (101 a), each of said carry select adder (101 a-1 ) circuit includes said cumulative carry propagate signal generating means (106), said cumulative carry generate signal generating means (107) and said real sum signal generating means (108) made of combinations of logic gate circuits using CMOS transistors.

Claim 5

A binary operator according to claim 3, wherein said cumulative carry propagate signal generating means (106) comprises a four-inputs NAND circuit (161) and an inverter circuit (162), four inputs of said NAND circuit (161) are supplied with carry propagate signals (P 0 ~P 3 ), an output of said NAND circuit (161) is connected to an input of said inverter circuit (162), and said inverter circuit (162) outputs a cumulative carry propagate signal (BP 3 `).

Claim 6

A binary operator according to claim 3, wherein said cumulative carry generate signal generating means (107) comprises an inverter circuit (171), a two-inputs NAND circuit (172), a three-inputs NAND circuit (173) and a first and a second four-input NAND circuits(174, 175), an input of said inverter circuit (171) is supplied with a carry generate signal(G 3 ), a first input of said two-inputs NAND circuit (172) is supplied with a carry generate signal(G 2 ) and a second input of said two-inputs NAND circuit (172) is supplied with a carry propagate signal (P 3 ), a first input of said three-inputs NAND circuit (173) is supplied with a carry generate signal (G 1 ) and a second and a third inputs of said three-inputs NAND circuit (173) are supplied with carry propagate signals (P 2 , P 3 ), a first input of said first four-inputs NAND circuit (174) is supplied with a carry generate signal (Go) and a second, a third and a fourth inputs of said first four-inputs NAND circuit (174) are supplied with carry propagate signals (P 1 ~P 3 ), outputs of said inverter circuit (171), said two-inputs NAND circuit (172), said three-inputs NAND circuit (173) and said first four-input NAND circuit (174) are connected to four inputs of said second four-input NAND circuit (175), and said second four-input NAND circuit (175) outputs a cumulative carry generate signal (BG 3 * ).

Claim 7

A binary operator according to claim 3, wherein said real sum signal generating means (108) comprises a NOR circuit (181) and a first and a second EOR circuits (182, 183), a first input of said NOR circuit (181) is supplied with an inverted real carry signal ( and a second input of said NOR circuit (181) is supplied with an inverted cumulative carry propagate signal ( BP 2 * ), a first input of said first EOR circuit (182) is supplied with a carry propagate signal (P 3 ) and a second input of said first EOR circuit (182) is supplied with a cumulative carry generate signal (BG2 * ), an output of said first EOR circuit (182) is connected to a first input of said second EOR circuit (183) and an output of said NOR circuit (181) is connected to a second input of said second EOR circuit(183), and said second EOR circuit (183) outputs a real sum signal (F 3 ).

Claim 8

A binary operator according to claim 1, wherein said real sum signal generating means (108) comprises an EOR circuit(1811), an ENOR circuit (1812), a first and a second transfer gate circuits (1813, 1814) and an inverter circuit (1815), a first input of said EOR circuit (1811) is supplied with a cumulative carry propagate signal (BP i-1 *), a first input of said ENOR circuit (1812) is supplied with a cumulative carry generate signal (BG i-1 *) and a second input of said ENOR circuit (1812) is supplied with a carry propagate signal (P ; ), an output of said EOR circuit (1811) is connected to an input of said first transfer gate circuit (1813) and an output of said ENOR circuit(1812) is connected to a second input of said EOR circuit (1811) and an input of said second transfer gate circuit (1814), a first control gate of said first transfer gate circuit (1813) and a second control gate of said second transfer gate circuit (1814) are connected and supplied with a real carry signal (C M-1 ), a second control gate of said first transfer gate circuit (1813) and a first control gate of said second transfer gate circuit (1814) are connected and supplied with an inverted real carry signal ( outputs of said first and second transfer gate circuits (1813, 1814) are commonly connected to an input of said inverter circuit (1815), and said inverter circuit (1815) outputs a real sum signal (F ; ).

Claim 9

A binary operator according to claim 1, wherein said real sum signal generating means (108) comprises a NOR circuit (1821), an inverter circuit (1822), a first and a second transfer gate circuits (1823, 1824) and an ENOR circuit (1825), a first input of said NOR circuit (1821) is supplied with a cumulative carry propagate signal (BP i-1 *), a second input of said NOR circuit (1821) and an input of said inverter circuit (1822) are connected and supplied with a cumulative carry generate signal (BG i-1 *), an output of said NOR circuit (1821) is connected to an input of said first transfer gate circuit (1823) and an output of said inverter circuit (1822) is connected to an input of said second transfer gate circuit (1824), a first control gate of said first transfer gate circuit (1823) and a second control gate of said second transfer gate circuit (1824) are connected and supplied with a real carry signal (C M-1 ), a second control gate of said first transfer gate circuit (1823) and a first control gate of said second transfer gate circuit (1824) are connected and supplied with an inverted real carry signal ( C M-1 ), outputs of said first and second transfer gate circuits (1823, 1824) are commonly connected to a first input of said ENOR circuit (1825) and a second input of said ENOR circuit (1825) is supplied with a carry propagate signal (P,) and said ENOR circuit (1825) outputs a real sum signal (F,).

Claim 10

A binary operator according to claim 1, wherein said real sum signal generating means (108) comprises an AND circuit (1831), a NOR circuit (1832) and an ENOR circuit (1833), a first input of said AND circuit (1831) is supplied with a cunulative carry propagate signal (BP i-1 *), a second input of said AND circuit (1831) is supplied with a real carry signal (C M . i ) and an output of said AND circuit (1831) is connected to a first input of said NOR circuit (1832), a second input of said NOR circuit (1832) is supplied with a cumulative carry generate signal (BG i-1 *), a first input of said ENOR circuit (1833) is supplied with a carry propagate signal (P i ) and an output of said NOR circuit (1832) is connected to a second input of said ENOR circuit (1833), and said ENOR circuit (1833) outputs a real sum signal (F ; ).

Claim 11

A binary operator according to claim 1, wherein said real sum signal generating means (108) comprises a NAND circuit (1841), an EOR circuit (1842) and an ENOR circuit (1843), a first input of said NAND circuit (1841) is supplied with a real carry signal (C M-1 ) and a second input of said NAND circuit (1841) is supplied with a cumulative carry propagate signal (BP i-1 *), a first input of said EOR circuit (1842) is supplied with a cumulative carry generate signal (BG i-1 *) and a second input of said EOR circuit (1842) is supplied with a carry propagate signal (P ; ), an output of said NAND circuit (1841) is connected to a first input of said ENOR circuit (1843) and an output of said EOR circuit (1842) is connected to a second input of said ENOR circuit (1843), and said ENOR circuit (1843) outputs a real sum signal (F i ).

Claim 12

A binary operator according to claim 1, wherein said real sum signal generating means (108) comprises a NAND circuit (1851), an EOR circuit (1852), a first, a second and a third inverter circuits (1853 1854) and a first and a second mutually connected with a transfer gate circuit and an inverter circuit.

Claim 13

A binary operator according to claim 1, wherein said cumulative carry propagate signal generating means (106) comprises a chain circuit mutually connected with a transfer gate circuit and an inverter circuit.

Claim 14

A binary operator according to claim 1, wherein said cumulative carry generate signal generating means (107) comprises a chain circuit mutually connected with a transfer gate circuit and an inverter circuit.

Claim 15

A binary operator, having a borrow propagate signal and borrow generate signal generating means (200) which receives two pieces of n-bit binary data (A, B) and generates a borrow propagate signal (P;) and a borrow generate signal (G ; ) of various digits, said two pieces of n-bit binary data are divided into blocks of predetermined number of bits, each data (A, B) of said divided blocks is processed in parallel by a plurality of block subtracters based on the corresponding borrow propagate signal (P ; ) and borrow generate signal (G;), and a real difference signal (F,) is output by calculating the arithmetic difference of said two n-bit binary data (A, B), wherein said binary operator comprises: a cumulative borrow propagate signal generating means (206), connected to said borrow propagate signal and borrow generate signal generating means (200) and receiving borrow propagate signals (P M ~P i-1 ) of the various digits in said block subtracters, for generating a cumulative borrow propagate signal BP i-1 *) by calculating said borrow propagate signals (P M ~P i-1 ); a cumulative borrow generate signal generating means (207), connected to said borrow propagate signal and borrow generate signal generating means (200) and receiving the borrow propagate signals (P M ~P i-1 ) and borrow generate signals (G M ~G i-1 ) of the various digits in said block subtracters, for generating a cumulative borrow generate signal (BG.-1 * ) by calculating said borrow propagate signals (P M ~P i-1 ) and said borrow generate signals (G M ~G i-1 ); a real difference signal generating means (208), connected to said borrow propagate signal and borrow generate signal generating means (200), said cumulative borrow propagate signal generating means (206) and said cumulative borrow generate signal generating means (207) and receiving the borrow propagate signal (P ; ) of various digits, the cumulative borrow propagate signal (BP i-1 *) from said cumulative borrow propagate signal generating means (206), the cumulative borrow generate signal (BG i-1 *) from said cumulative borrow generate signal generating means (207) and a real borrow signal (C m . 1 ), for generating the real difference signal (F,) by calculating said borrow propagate signal (P ; ), said cumulative borrow propagate signal (BP i-1 *), said cumulative borrow generate signal (BG i . I ') and said real borrow signal (C M-1 ).

Claim 16

A binary operator, having a borrow propagate signal and borrow generate signal generating means (200) which receives two pieces of n-bit binary data (A, B) and generates a borrow propagate signal (P;) and a borrow generate signal (G ; ) of various digits, said two pieces of n-bit binary data are divided into blocks of predetermined number of bits, each data (A, B) of said divided blocks is processed in parallel by a plurality of block subtracters based on the corresponding borrow propagate signal (P ; ) and borrow generate signal (G;), and a real difference signal (F,) is output by calculating the arithmetic difference of said two n-bit binary data (A, B), wherein said binary operator comprises: a cumulative borrow propagate signal generating means (206), connected to said borrow propagate signal and borrow generate signal generating means (200) and receiving borrow propagate signals (P M ~P i-1 ) of the various digits in said block subtracters, for generating a cumulative borrow propagate signal BP i-1 *) by calculating said borrow propagate signals (P M ~P i-1 ); a cumulative borrow generate signal generating means (207), connected to said borrow propagate signal and borrow generate signal generating means (200) and receiving the borrow propagate signals (P M ~P i-1 ) and borrow generate signals (G M ~G i-1 ) of the various digits in said block subtracters, for generating a cumulative borrow generate signal (BG.-1 * ) by calculating said borrow propagate signals (P M ~P i-1 ) and said borrow generate signals (G M ~G i-1 ); a real difference signal generating means (208), connected to said borrow propagate signal and borrow generate signal generating means (200), said cumulative borrow propagate signal generating means (206) and said cumulative borrow generate signal generating means (207) and receiving the borrow propagate signal (P ; ) of various digits, the cumulative borrow propagate signal (BP i-1 *) from said cumulative borrow propagate signal generating means (206), the cumulative borrow generate signal (BG i-1 *) from said cumulative borrow generate signal generating means (207) and a real borrow signal (C m . 1 ), for generating the real difference signal (F,) by calculating said borrow propagate signal (P ; ), said cumulative borrow propagate signal (BP i-1 *), said cumulative borrow generate signal (BG i . I ') and said real borrow signal (C M-1 ).

Claim 17

A binary operator according to claim 14, wherein an i-th digit of said real difference signal generating means (208) generates the real difference signal (F ; ) of said i-th digit by calculating the borrow propagate signal (P,) of said i-th digit, the cumulative borrow propagate signal (BP i-1 *) of said (i-1)-th digit, the cumulative borrow generate signal (BG i-1 *) of said (i-1)-th digit and a real borrow signal (C M . I ) advanced from the lower digit to the block subtracter to which it belongs.

Claim 18

A binary operator according to claim 14, wherein said binary operator comprises a plurality of borrow select subtracter circuits, each of said borrow select subtracter circuit includes said cumulative borrow propagate signal generating means (206), said cumulative borrow generate signal generating means (207) and said real difference signal generating means (208) made of combinations of logic gate circuits using CMOS transistors.

Claim 19

A binary operator according to claim 16, wherein said cumulative borrow propagate signal generating means (206) comprises a four-input NAND circuit and an inverter circuit, four inputs of said NAND circuit are supplied with borrow propagate signals, an output of said NAND circuit is connected to an input of said inverter circuit, and said inverter circuit outputs a cumulative borrow propagate signal.

Claim 20

A binary operator according to claim 16, wherein said cumulative borrow generate signal generating means (207) comprises an inverter circuit, a two-inputs NAND circuit, a three-inputs NAND circuit and a first and a second four-input NAND circuits, an input of said inverter circuit is supplied with a borrow generate signal, a first input of said two-inputs NAND circuit is supplied with a borrow generate signal and a second input of said two-inputs NAND circuit is supplied with a borrow propagate signal, a first input of said three-inputs NAND circuit is supplied with a borrow generate signal and a second and a third inputs of said three-inputs NAND circuit are supplied with borrow propagate signals, a first input of said first four-inputs NAND circuit is supplied with a borrow generate signal and a second, a third and a fourth inputs of said first four-inputs NAND circuit are supplied with borrow propagate signals, outputs of said inverter circuit, said two-inputs NAND circuit, said three-inputs NAND circuit and said first four-input NAND circuit are connected to four inputs of said second four-input NAND circuit, and said second four-input NAND circuit outputs a cumulative borrow generate signal.

Claim 21

A binary operator according to claim 16, wherein said real difference signal generating means (208) comprises a NOR circuit, an EOR circuit and an ENOR circuit, a first input of said NOR circuit is supplied with an inverted real borrow signal and a second input of said NOR circuit is supplied with an inverted cumulative borrow propagate signal, a first input of said EOR circuit is supplied with a borrow propagate signal and a second input of said first EOR circuit is supplied with a cumulative borrow generate signal, an output of said first EOR circuit is connected to a first input of said ENOR circuit and an output of said NOR circuit is connected to a second input of said ENOR circuit, and said ENOR circuit outputs a real difference signal.

Claim 22

A binary operator according to claim 14, wherein said real difference signal generating means (208) comprises a first and a second EOR circuits, a first and a second transfer gate circuits and an inverter circuit, a first input of said first EOR circuit is supplied with a cumulative borrow propagate signal, a first input of said second EOR circuit is supplied with a cumulative borrow generate signal and a second input of said second EOR circuit is supplied with a borrow propagate signal, an output of said first EOR circuit is connected to an input of said first transfer gate circuit and an output of said second EOR circuit is connected to a second input of said first EOR circuit and an input of said second transfer gate circuit, a first control gate of said first transfer gate circuit and a second control gate of said second transfer gate circuit are connected and supplied with a real borrow signal, a second control gate of said first transfer gate circuit and a first control gate of said second transfer gate circuit are connected and supplied with an inverted real borrow signal, outputs of said first and second transfer gate circuits are commonly connected to an input of said inverter circuit, and said inverter circuit outputs a real difference signal.

Claim 23

A binary operator according to claim 14, wherein said real difference signal generating means (208) comprises a NOR circuit, an inverter circuit, a first and a second transfer gate circuits and an EOR circuit, a first input of said NOR circuit is supplied with a cumulative borrow propagate signal, a second input of said NOR circuit and an input of said inverter circuit are connected and supplied with a cumulative borrow generate signal, an output of said NOR circuit is connected to an input of said first transfer gate circuit and an output of said inverter circuit is connected to an input of said second transfer gate circuit, a first control gate of said first transfer gate circuit and a second control gate of said second transfer gate circuit are connected and supplied with a real borrow signal, a second control gate of said first transfer gate circuit and a first control gate of said second transfer gate circuit are connected and supplied with an inverted real borrow signal, outputs of said first and second transfer gate circuits are commonly connected to a first input of said EOR circuit and a second input of said EOR circuit is supplied with a borrow propagate signal, and said EOR circuit outputs a real difference signal.

Claim 24

A binary operator according to claim 14, wherein said real difference signal generating means (208) comprises an AND circuit, a NOR circuit and an EOR circuit, a first input of said AND circuit is supplied with a cumulative borrow propagate signal, a second input of said AND circuit is supplied with a real borrow signal and an output of said AND circuit is connected to a first input of said NOR circuit, a second input of said NOR circuit is supplied with a cumulative borrow generate signal, a first input of said EOR circuit is supplied with a borrow propagate signal and an output of said NOR circuit is connected to a second input of said EOR circuit, and said EOR circuit outputs a real difference signal.

Claim 25

A binary operator according to claim 14, wherein said real difference signal generating means (208) comprises a NAND circuit, a first and second EOR circuits, a first input of said NAND circuit is supplied with a real carry signal and a second input of said NAND circuit is supplied with a cumulative borrow propagate signal, a first input of said first EOR circuit is supplied with a cumulative borrow generate signal and a second input of said first EOR circuit is supplied with a borrow propagate signal, an output of said NAND circuit is connected to a first input of said second EOR circuit and an output of said first EOR circuit is connected to a second input of said second EOR circuit, and said second EOR circuit outputs a real difference signal.

Claim 26

A binary operator according to claim 14, wherein said real difference signal generating means comprises a NAND circuit, an ENOR circuit, a first, a second and a third inverter circuits and a first and a second transfer gate circuits, a first input of said NAND circuit is supplied with a real borrow signal and a second input of said NAND circuit is supplied with a cumulative borrow propagate signal, a first input of said ENOR circuit is supplied with a cumulative borrow generate signal and a second input of said ENOR circuit is supplied with a borrow propagate signal, an output of said NAND circuit is commonly connected to an input of said first inverter circuit, a second control gate of said first transfer gate circuit and a first control gate of said second transfer gate circuit, an output of said ENOR circuit is commonly connected to an input of said second inverter circuit and an input of said first transfer gate circuit, an output of said first inverter circuit is commonly connected to a first control gate of said first transfer gate circuit and a second control gate of said second transfer gate circuit, an output of said second inverter circuit is connected to an input of said second transfer gate circuit, outputs of said first and second transfer gate circuits are commonly connected to an input of said third inverter circuit, and said third inverter circuit outputs a real difference signal.

Claim 27

A binary operator according to claim 14, wherein said cumulative borrow propagate signal generating means (206) comprises a chain circuit mutually connected with a transfer gate circuit and an inverter circuit.

Claim 28

A binary operator according to claim 14, wherein said cumulative borrow generate signal generating means (207) comprises a chain circuit mutually connected with a transfer gate circuit and an inverter circuit.

Claim 29

A binary operator comprises: a carry propagate signal and carry generate signal generating means (100), receiving two pieces of n-bit binary data (A, B), for generating a carry propagate signal (P ; ) and a carry generate signal (G ; ) of various digits; a block addition means (101), connected to said carry propagate signal and carry generate signal generating means (100) and receiving a real carry signal (C M . i ) and the carry propagate signal (PM-Pi) and the carry generate signal (GM-G;) from said carry propagate signal and carry generate signal generating means (100), for dividing said two pieces of n-bit binary data (A, B) into block of predetermined number of bits, processing in parallel based on the carry propagate signal (P M -P i ) and the carry generate signal (G M -G;) corresponding to each data of said divided blocks and generating a real sum signal (F,) by calculating the arithmetic sum of said two n-bit binary data (A, B); a block carry propagate signal and block carry generate signal generating means (103), connected to said carry propagate signal and carry generate signal generating means (100) and receiving the carry propagate signal (P M ~P M-1 ) and the carry generate signal (G M ~G M-1 ) from said carry propagate signal and carry generate signal generating means (100), for generating a block carry propagate signal (BP M ~BP M-1 ) and a block carry generate signal (BP M ~BP M-1 ) by the carry propagate signal (P M ~P M-1 ) and the carry generate signal (G M ~G M-1 ) corresponding to each data of said divided blocks; a cumulative block carry propagate signal and cumulative block carry generate signal generating means (116), connected to said block carry propagate signal and block carry generate signal generating means (103) and receiving the block carry propagate signal (BP M '-BP M . i ) and the block carry generate signal (BG M ~BG M-1 ) from said block carry propagate signal and block carry generate signal generating means (103), for generating a cumulative block carry propagate signal (CP M-1 *) and a cumulative block carry generate signal (CG M-1 *) by the block carry propagate signal (BP M ~BP M-1 ) and the block carry generate signal (BG M ~BG M-1 ); and a real carry signal generating means (117), connected to said cumulative block carry propagate signal and cumulative block carry generate signal generating means (116) and said block addition means (101) and receiving a carry signal (C M ' -m '), the cumulative block carry propagate signal (CP M-1 *) and the cumulative block carry generate signal (CG M-1 *) from said cumulative block carry propagate signal and cumulative block carry generate signal generating means (116), for generating a real carry signal (C M . I ) by the carry signal (C M-m '), the cumulative block carry propagate signal (CP M-1 *) and the cumulative block carry generate signal CG M-1 *).

Claim 30

A binary operator comprises: a carry propagate signal and carry generate signal generating means (100), receiving two pieces of n-bit binary data (A, B), for generating a carry propagate signal (P ; ) and a carry generate signal (G ; ) of various digits; a block addition means (101), connected to said carry propagate signal and carry generate signal generating means (100) and receiving a real carry signal (C M . i ) and the carry propagate signal (PM-Pi) and the carry generate signal (GM-G;) from said carry propagate signal and carry generate signal generating means (100), for dividing said two pieces of n-bit binary data (A, B) into block of predetermined number of bits, processing in parallel based on the carry propagate signal (P M -P i ) and the carry generate signal (G M -G;) corresponding to each data of said divided blocks and generating a real sum signal (F,) by calculating the arithmetic sum of said two n-bit binary data (A, B); a block carry propagate signal and block carry generate signal generating means (103), connected to said carry propagate signal and carry generate signal generating means (100) and receiving the carry propagate signal (P M ~P M-1 ) and the carry generate signal (G M ~G M-1 ) from said carry propagate signal and carry generate signal generating means (100), for generating a block carry propagate signal (BP M ~BP M-1 ) and a block carry generate signal (BP M ~BP M-1 ) by the carry propagate signal (P M ~P M-1 ) and the carry generate signal (G M ~G M-1 ) corresponding to each data of said divided blocks; a cumulative block carry propagate signal and cumulative block carry generate signal generating means (116), connected to said block carry propagate signal and block carry generate signal generating means (103) and receiving the block carry propagate signal (BP M '-BP M . i ) and the block carry generate signal (BG M ~BG M-1 ) from said block carry propagate signal and block carry generate signal generating means (103), for generating a cumulative block carry propagate signal (CP M-1 *) and a cumulative block carry generate signal (CG M-1 *) by the block carry propagate signal (BP M ~BP M-1 ) and the block carry generate signal (BG M ~BG M-1 ); and a real carry signal generating means (117), connected to said cumulative block carry propagate signal and cumulative block carry generate signal generating means (116) and said block addition means (101) and receiving a carry signal (C M ' -m '), the cumulative block carry propagate signal (CP M-1 *) and the cumulative block carry generate signal (CG M-1 *) from said cumulative block carry propagate signal and cumulative block carry generate signal generating means (116), for generating a real carry signal (C M . I ) by the carry signal (C M-m '), the cumulative block carry propagate signal (CP M-1 *) and the cumulative block carry generate signal CG M-1 *).

Claim 31

A binary operator according to claim 27, wherein said block addition means (101) generates presumed sum signals in the case of the carry signal output from said real carry signal generating means being "0" and "1 ", and selects one of said presumed sum signals in accordance with the content of the real carry signal (C M .,) from said real carry signal generating means (117).

Claim 32

A binary operator according to claim 27, wherein said binary operator comprises a plurality of block look ahead carry generator circuits (105a), each of said block look ahead carry generator circuit (105 a-1 ) includes said cumulative block carry propagate signal and cumulative block carry generate signal generating: means (116) and said real carry signal generating means (117) made of combinations of logic gate circuits and transfer gate circuits using CMOS transistors.

Claim 33

A binary operator according to claim 29, wherein said real carry signal generating means (117) comprises a NOR circuit (1171). a first and a second inverter circuits (1172, 1173) and a first and a second transfer gate circuits 1174, 1175), an input of said first inverter circuit (1172) and a first input of said NOR circuit (1171) are connected and supplied with a cumulative block carry generate signal (CG15*), a second input of said NOR circuit (1171) is supplied with a cumulative block carry propagate signal (CP 15 *), an output of said first inverter circuit (1172) is connected to an input of said first transfer gate circuit (1174) and . an output of said NOR circuit (1171) is connected to an input of said second transfer gate circuit (1175), a first control gate of said first transfer gate circuit (1174) and a second control gate of said second transfer gate circuit (1175) are connected and supplied with an inverted real carry signal ( C -1 ) , a second control gate of said first transfer gate circuit (1174) and a first control gate of said second transfer gate circuit (1175) are connected and supplied with a real carry signal (C -i ), outputs of said first and second transfer gate circuits (1174, 1175) are commonly connected to an input of said second inverter circuit (1173), and said second inverter circuit (1173) outputs a real carry signal (C 15 ).

Claim 34

A binary operator according to claim 29, wherein said block look ahead carry generator circuit (105a) comprises an AND circuit (1511), a NOR circuit (1512) and an inverter circuit (1513), a first input of said AND circuit (1511) is supplied with a real carry signal (C M '- m '), a second input of said AND circuit (1511) is supplied with a cumulative block carry propagate signal (CP,') and an output of said AND circuit (1511) is connected to a first input of said NOR circuit (1512), a second input of said NOR circuit (1512) is supplied with a cumulative block carry generate signal (CG i *), an output of said NOR circuit (1512) is connected to an input of said inverter circuit (1513), and said inverter circuit (1513) outputs a real carry signal (C).

Claim 35

A binary operator according to claim 29, wherein said block look ahead carry generator circuit (105a) comprises a NOR circuit (1521), a first and a second inverter circuits (1522, 1523) and a first and a second transfer gate circuits (1524, 1525), a first input of said NOR circuit (1521) is supplied with a cumulative block carry propagate signal (CP,'), a second input of said NOR circuit (1521) and an input of said first inverter circuit (1522) are connected and supplied with a cumulative block carry generate signal (CG i *), an output of said NOR circuit (1521) is connected to an input of said first transfer gate circuit (1524) and an output of said first inverter circuit (1522) is connected to an input of said second transfer gate circuit (1525), a first control gate of said first transfer gate circuit (1524) and a second control gate of said second transfer gate circuit (1525) are connected and supplied with a real carry signal (C M ' -m '), a second control gate of said first transfer gate circuit (1524) and a first control gate of said second transfer gate circuit (1525) are connected and supplied with an inverted real carry signal ( C M-m ), outputs of said first and second transfer gate circuits (1524, 1525) are commonly connected to an input of said second inverter circuit (1523), and said second inverter circuit (1523) outputs a real carry signal (C ; ).

Claim 36

A binary operator according to claim 29, wherein said block look ahead carry generator circuit (105a) comprises a EOR circuit (1531), a first and second inverter circuits (1532, 1533) and a first and a second transfer gate circuits (1534, 1535), a first input of said EOR circuit (1531) is supplied with a cumulative block carry propagate signal (CP ; * ) and an output of said EOR circuit (1531) is connected to an input of said first transfer gate circuit (1534), an input of said first inverter circuit (1532) is supplied with a cumulative block carry generate signal (CG, * ) and an output of said first inverter circuit (1532) and a second input of said EOR circuit (1531) are commonly connected to an input of said second transfer gate circuit (1535), a first control gate of said first transfer gate circuit (1534) and a second control gate of said second transfer gate circuit (1535) are connected and supplied with a real carry signal (C M ' -m '), a second control gate of said first transfer gate circuit (1534) and a first control gate of said second transfer gate circuit (1535) are connected and supplied with an inverted real carry signal ( C M-m ), outputs of said first and second transfer gate circuits (1534, 1535) are commonly connected to an input of said second inverter circuit (1533), and said second inverter circuit (1533) outputs a real carry signal (C ; ).

Claim 37

A binary operator according to claim 29, wherein said block look ahead carry generator circuit (105a) comprises a NAND circuit (1541) and an ENOR circuit (1542), a first input of said NAND circuit (1541) is supplied with a real carry signal (C M '- m ') and a second input of said NAND circuit (1541) is supplied with a cumulative block carry propagate signal (CP i *), an output of said NAND circuit (1541) is connected to a first input of said ENOR circuit (1542) and a second input of said ENOR circuit (1542) is supplied with a cumulative block carry generate signal (CG i *), and said ENOR circuit (1542) outputs a real carry signal (C,).

Claim 38

A binary operator according to claim 29, wherein said block look ahead carry generator circuit (105a) comprises a NAND circuit (1551), a first, a second and a third inverter circuits (1552 1554) and a first and a second transfer gate circuits (1555, 1556), a first input of said NAND circuit (1551) is supplied with a . real carry signal (C M ' -m ') and a second input of said NAND circuit (1551) is supplied with a cumulative block carry propagate signal (CP i *), an output of said NAND circuit (1551) is connected to an input of said first inverter circuit (1552) and a second control gate of said first transfer gate circuit (1555) and a first control gate of said second transfer gate circuit (1556), an output of said first inverter circuit (1552) is connected to a first control gate of said first transfer gate circuit (1555) and a second control gate of said second transfer gate circuit (1556), an input of said second inverter circuit (1553) and an input of said first transfer gate circuit (1555) are connected and supplied with a cumulative block carry generate.signal (CG i *), an output of said second inverter circuit (1553) is connected to an input of said second transfer gate circuit (1556), outputs of said first and second transfer gate circuits (1555, 1556) are commonly connected to an input of said third inverter circuit (1554), and said third inverter circuit (1554) outputs a real carry signal (C;).

Claim 39

A binary operator according to claim 29, wherein said block look ahead carry generator circuit (105a) comprises a first and a second transfer gate circuits (1561, 1562) and an inverter circuit (1563), an input of said first transfer gate circuit is supplied with an inverted real carry signal (C M ' -m '), an input of said second transfer gate circuit (1562) is supplied with an inverted cumulative block carry generate signal (CG i *), a first control gate of said first transfer gate circuit (1561) and a second control gate of said second transfer gate circuit (1562) are connected and supplied with a cumulative block carry propagate signal (CP i *), a second control gate of said first transfer gate circuit (1561) and a first control gate of said second transfer gate circuit (1562) are connected and supplied with an inverted cumulative block carry propagate signal (CP, * ), outputs of said first and second transfer gate circuits (1561, 1562) are commonly connected to an input of said inverter circuit (1563), and said inverter circuit (1563) outputs a real carry signal (C i ).

Claim 40

A binary operator according to claim 27, wherein said binary operator comprises a plurality of block look ahead carry generator circuits (105 b ) made of a chain circuit mutually connected with a transfer gate circuit and an inverter circuit.

Claim 41

A binary operator according to claim 27, wherein said said binary operator comprises a plurality of block look ahead carry generator circuit (105 c , 105 d ) constructed by one or more stages.

Claim 42

39,. A binary operator comprises: a borrow propagate signal and borrow generate signal generating means (200), receiving two pieces of n-bit binary data (A, B), for generating a borrow propagate signal (P ; ) and a borrow generate signal (G,) of various digits; a block subtraction means (201), connected to said borrow propagate signal and borrow generate signal generating means (200) and receiving a real borrow signal (C M-1 ) and the borrow propagate signal (P M P,) and the borrow generate signal (G M G;) from said borrow propagate signal and borrow generate signal generating means (200), for dividing said two pieces of n-bit binary data (A, B) into blocks of predetermined number of bits, processing in parallel based on the borrow propagate signal (P M P i ) and the borrow generate signal (G M G;) corresponding to each data of said divided blocks and generating a real difference signal (F ; ) by calculating the arithmetic difference of said two n-bit binary data (A, B); a block borrow propagate signal and block borrow generate signal generating means (203), connected to said borrow propagate signal and borrow generate signal generating means (200) and receiving the borrow propagate signal (P M ' P M-1 ) and the borrow generate signal (G M ' G M-1 ) from said borrow propagate signal and borrow generate signal generating means (200), for generating a block borrow propagate signal (BP M ' BP M-1 ) and a block borrow generate signal (BG M ' BG M-1 ) by the borrow propagate signal (P M ' P M-1 ) and the borrow generate signal (G M ' G M-1 ) corresponding to each data of said divided blocks; a cumulative block borrow propagate signal and cumulative block borrow generate signal generating means (216), connected to said block borrow propagate signal and block borrow generate signal generating means (203) and receiving the block borrow propagate signal (BP M ' BP M . i ) and the block borrow generate signal, from said block borrow propagate signal (BG M ' BG M-1 ) and block borrow generate signal generating means (203), for generating a cumulative block borrow propagate signal (CP M-1 *) and a cumulative block borrow generate signal (CG M-1 *) by the block borrow propagate signal (BP M ' BP M . i ) and the block borrow generate signal (BG M ' BG M-1 ); and a real borrow signal generating means (217), connected to said cumulative block borrow propagate signal and cumulative block borrow generate signal generating means (216) and said block subtraction means (201) and receiving a borrow signal (C M ' -m '), the cumulative block borrow propagate signal (CP M-1 *) and the cumulative block borrow generate signal (CG M-1 *) from said cumulative block borrow propagate signal and cumulative block borrow generate signal generating means (216), for generating a real borrow signal (C M-1 ) by the borrow signal (C M ' -m '), the cumulative block borrow propagate signal (CP M-1 *) and the cumulative block borrow generate signal (CG M-1 *).

Claim 43

39,. A binary operator comprises: a borrow propagate signal and borrow generate signal generating means (200), receiving two pieces of n-bit binary data (A, B), for generating a borrow propagate signal (P ; ) and a borrow generate signal (G,) of various digits; a block subtraction means (201), connected to said borrow propagate signal and borrow generate signal generating means (200) and receiving a real borrow signal (C M-1 ) and the borrow propagate signal (P M P,) and the borrow generate signal (G M G;) from said borrow propagate signal and borrow generate signal generating means (200), for dividing said two pieces of n-bit binary data (A, B) into blocks of predetermined number of bits, processing in parallel based on the borrow propagate signal (P M P i ) and the borrow generate signal (G M G;) corresponding to each data of said divided blocks and generating a real difference signal (F ; ) by calculating the arithmetic difference of said two n-bit binary data (A, B); a block borrow propagate signal and block borrow generate signal generating means (203), connected to said borrow propagate signal and borrow generate signal generating means (200) and receiving the borrow propagate signal (P M ' P M-1 ) and the borrow generate signal (G M ' G M-1 ) from said borrow propagate signal and borrow generate signal generating means (200), for generating a block borrow propagate signal (BP M ' BP M-1 ) and a block borrow generate signal (BG M ' BG M-1 ) by the borrow propagate signal (P M ' P M-1 ) and the borrow generate signal (G M ' G M-1 ) corresponding to each data of said divided blocks; a cumulative block borrow propagate signal and cumulative block borrow generate signal generating means (216), connected to said block borrow propagate signal and block borrow generate signal generating means (203) and receiving the block borrow propagate signal (BP M ' BP M . i ) and the block borrow generate signal, from said block borrow propagate signal (BG M ' BG M-1 ) and block borrow generate signal generating means (203), for generating a cumulative block borrow propagate signal (CP M-1 *) and a cumulative block borrow generate signal (CG M-1 *) by the block borrow propagate signal (BP M ' BP M . i ) and the block borrow generate signal (BG M ' BG M-1 ); and a real borrow signal generating means (217), connected to said cumulative block borrow propagate signal and cumulative block borrow generate signal generating means (216) and said block subtraction means (201) and receiving a borrow signal (C M ' -m '), the cumulative block borrow propagate signal (CP M-1 *) and the cumulative block borrow generate signal (CG M-1 *) from said cumulative block borrow propagate signal and cumulative block borrow generate signal generating means (216), for generating a real borrow signal (C M-1 ) by the borrow signal (C M ' -m '), the cumulative block borrow propagate signal (CP M-1 *) and the cumulative block borrow generate signal (CG M-1 *).

Claim 44

A binary operator according to claim 39, wherein said block subtraction means (201) generates presumed difference signals in the cases of the borrow signal output from said real borrow signal generating means being "0" and "1 ", and selects one of said presumed difference signals in accordance with the content of the real borrow signal (C M . i ) from said real borrow signal generating means (217).

Claim 45

A binary operator according to claim 39, wherein said binary operator comprises a plurality of block look ahead borrow generator circuits (105a), each of said block look ahead borrow generator circuit (105 a-1 ) includes said cumulative block borrow propagate signal and cumulative block borrow generate signal generating means (216) and said real borrow signal generating means (217) made of combinations of logic gate circuits and transfer gate circuits using CMOS transistors.

Claim 46

A binary operator according to claim 41, wherein said real borrow signal generating means (217) comprises a NOR circuit, a first and a second inverter circuits and a first and a second transfer gate circuits, an input of said first inverter circuit and a first input of said NOR circuit are connected and supplied with a cumulative block borrow generate signal, a second input of said NOR circuit is supplied with a cumulative block borrow propagate signal, an output of said first inverter circuit is connected to an input of said first transfer gate circuit and an output of said NOR circuit is connected to an input of said second transfer gate circuit, a first control gate of said first transfer gate circuit and a second control gate of said second transfer gate circuit are connected and supplied with an inverted real borrow signal, a second control gate of said first transfer gate circuit and a first control gate of said second transfe,gate circuit are connected and supplied with a real borrow signal, outputs of said first and second transfer gate circuits are commonly connected to an input of said second inverter circuit, and said second inverter circuit outputs a real borrow signal.

Claim 47

A binary operator according to claim 41, wherein said block look ahead borrow generator circuit (105a) comprises an AND circuit, a NOR circuit and an inverter circuit, a first input of said AND circuit is supplied with a real borrow signal, a second input of said AND circuit is supplied with a cumulative block borrow propagate signal and an output of said AND circuit is connected to a first input of said NOR circuit, a second input of said NOR circuit is supplied with a cumulative block borrow generate signal, an output of said NOR circuit is connected to an input of said inverter circuit, and said inverter circuit outputs a real borrow signal.

Claim 48

A binary operator according to claim 41, wherein said block look ahead'borrow generator circuit (105a) comprises a NOR circuit, a first and a second inverter circuits and a first and a second transfer gate circuits, a first input of said NOR circuit is supplied with a cumulative block borrow propagate signal, a second input of said NOR circuit and an input of said first inverter circuit are connected and supplied with a cumulative block borrow generate signal, an output of said NOR circuit is connected to an input of said first transfer gate circuit and an output of said first inverter circuit is connected to an input of said second transfer gate circuit, a first control gate of said first transfer gate circuit and a second control gate of said second transfer gate circuit are connected and supplied with a real borrow signal, a second control gate of said first transfer gate circuit and a first control gate of said second transfer gate circuit are connected and supplied with an inverted real borrow signal, outputs of said first and second transfer gate circuits are commonly connected to an input of said second inverter circuit, and said second inverter circuit outputs a real borrow signal.

Claim 49

A binary operator according to claim 41, wherein said block look ahead borrow generator circuit (105a) comprises a EOR circuit, a first and a second inverter circuits and a first and a second transfer gate circuits, a first input of said EOR circuit is supplied with a cumulative block borrow propagate signal and an output of said EOR circuit is connected to an input of said first transfer gate circuit, an input of said first inverter circuit is supplied with a cumulative block borrow generate signal and an output of said first inverter circuit and a second input of said EOR circuit are commonly connected to an input of said second transfer gate circuit, a first control gate of said first transfer gate circuit and a second control gate of said second transfer gate circuit are connected and supplied with a real borrow signal, a second control gate of said first transfer gate circuit and a first control gate of said second transfer gate circuit are connected and supplied with an inverted real borrow signal, outputs of said first and second transfer gate circuits are commonly connected to an input of said second inverter circuit, and said second inverter circuit outputs a real borrow signal.

Claim 50

A binary operator according to claim 41, wherein said block look ahead borrow generator circuit (105a) comprises a NAND circuit and an ENOR circuit, a first input of said NAND circuit is supplied with a real borrow signal and a second input of said NAND circuit is supplied with a cumulative .block borrow propagate signal, an output of said NAND circuit is connected to a first input of said ENOR circuit and a second input of said ENOR circuit is supplied with a cumulative block borrow generate signal, and said ENOR circuit outputs a real borrow signal.

Claim 51

A binary operator according to claim 41, wherein said block look ahead borrow generator circuit 105a) comprises a NAND circuit, a first, a second and a third inverter circuits and a first and a second transfer gate circuits, a first input of said NAND circuit is supplied with a real borrow signal and a second input of said NAND circuit is supplied with a cumulative block borrow propagate signal, an output of said NAND circuit is connected to an input of said first inverter circuit and a second control gate of said first transfer gate circuit and a first control gate of said second transfer gate circuit, an output of said first inverter circuit is connected to a first control gate of said first transfer gate circuit and a second control gate of said second transfer gate circuit, an input of said second inverter circuit and an input of said first transfer gate circuit are connected and supplied with a cumulative block borrow generate signal, an output of said second inverter circuit is connected to an input of said second transfer gate circuit, outputs of said first and second transfer gate circuits are commonly connected to an input of said third inverter circuit, and said third inverter circuit outputs a real borrow signal.

Claim 52

A binary operator according to claim 41, wherein said block look ahead borrow generator circuit (105a) comprises a first and a second transfer gate circuits and an inverter circuit, an input of said first transfer gate circuit is supplied with an inverted real borrow signal, an input of said second transfer gate circuit is supplied with an inverted cumulative block borrow generate signal, a first control gate of said first transfer gate circuit and a second control gate of said second transfer gate circuit are connected and supplied with a cumulative block borrow propagate signal, a second control gate of said first transfer gate circuit and a first control gate of said second transfer gate circuit are connected and supplied with an inverted cumulative block borrow propagate signal, outputs of said first and second transfer gate circuits are commonly connected to an input of said inverter circuit, and said inverter circuit outputs a real borrow signal.

Claim 53

A binary operator according to claim 39, wherein said binary operator comprises a plurality of block look ahead borrow generator circuits (105 b ) made of a chain circuit mutually connected with a transfer gate circuit and an inverter circuit.

Claim 54

A binary operator according to claim 39, wherein said said binary operator comprises a plurality of block look ahead borrow generator circuits (105c, 105 d ) constructed by one or more stages.