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EP0346896A2
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A parallel-to-serial converter
Assignee: Fujitsu Ltd
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Filing: 1989-06-15
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Granted: —
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Expires: 2009-06-15
Abstract
Abstract A parallel-to-serial converter multiplexes parallel input data into a serial output data. This converter includes a multiplier(31) for multiplying an input clock corresponding to a parallel input data, a divider(34) for dividing the multiplied clock, and a waveform shaping circuit (32) for shaping a serial output data by the multiplied clock. The converter multiplexes parallel data at a center of each phase thereof based on the divided clock by adjusting phases between the input data (or the input clock) and the divided clock to be in a predetermined relationship.
Inventors
- 👤 Kazuo Yamane
- 👤 Masanori Shimasue
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 11:25
CPC Classifications
H; H03; H03M; H03M9/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
151 words
A parallel-to-serial converter for multiplexing a plurality of parallel input data into a serial data, comprising: (a) means for multiplying an input clock corresponding to the parallel input data and generating a multiple clock corresponding to the serial data; (b) means for dividing the multiple clock from said multiplying means and generating a divided clock corresponding to the parallel input data; (c) means for converting the parallel input data into a serial output data in accordance with the divided clock from said dividing means; (d) means for shaping a waveform of the serial data output from said converting means using the multiple clock from said multiplying means and outputting a multiplexed data; (e) means for comparing a phase relationship between the divided clock and the parallel input data; and (f) means for adjusting a phase relationship between the parallel input data and the divided clock in accordance with said comparing means.
Claim 2
Dependent Claim
151 words
A parallel-to-serial converter for multiplexing a plurality of parallel input data into a serial data, comprising: (a) means for multiplying an input clock corresponding to the parallel input data and generating a multiple clock corresponding to the serial data; (b) means for dividing the multiple clock from said multiplying means and generating a divided clock corresponding to the parallel input data; (c) means for converting the parallel input data into a serial output data in accordance with the divided clock from said dividing means; (d) means for shaping a waveform of the serial data output from said converting means using the multiple clock from said multiplying means and outputting a multiplexed data; (e) means for comparing a phase relationship between the divided clock and the parallel input data; and (f) means for adjusting a phase relationship between the parallel input data and the divided clock in accordance with said comparing means.
Claim 3
Dependent Claim
36 words
A parallel-to-serial converter according to claim 1, wherein said adjusting means controls said dividing means so that a phase of the divided clock is adjusted to be in a predetermined relationship with the parallel input data.
Claim 4
Dependent Claim
18 words
A parallel-to-serial converter according to claim 2, wherein said adjusting means inverses a polarity of the divided clock.
Claim 5
Dependent Claim
30 words
A parallel-to-serial converter according to claim 3 wherein said adjusting means inhibits the multiple clock to be input to said dividing means to inverse a polarity of an output thereof.
Claim 6
Dependent Claim
39 words
A parallel-to-serial converter according to claim 1, wherein said adjusting means controls phases of the parallel input data so that the phases of the parallel input data are adjusted to be in a predetermined relationship with the divided clock.
Claim 7
Dependent Claim
25 words
A parallel-to-serial converter according to claim 1, wherein said comparing means compares the phase of the divided clock with the phase of the input clock.
References Cited (Backward Citations)
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