Patent EP0346003A2 successfully refreshed from Google Patents.
EP0346003A2
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EP
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Multiprocessor control system
Assignee: Fujitsu Ltd
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Filing: 1989-06-01
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Granted: —
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Expires: 2009-06-01
Abstract
Abstract A multiprocessor control system adapted to a multiprocessor system includes a switching circuit (6, 25), a control stage circuit (4, 5, 7 - 9; 23, 24, 28 - 30), a switching mode setting circuit (11, 27), and a switching control circuit (10, 26). The switching circuit (6, 25) selectively switches the second group of instructions supplied from the first execution units to thereby select the second group of instructions relating to one of the plurality of first execution units. The control stage circuit (4, 5, 7 - 9; 23, 24, 28 - 30) includes a plurality of register stages used for controlling a pipeline process. The control stage circuit sequentially stores the second group of instructions relating to the selected one of the first execution units in the register stages and outputs, for every register stage, a state indicating signal indicating state information on the corresponding register stage. The switching mode setting circuit (11, 27) generates a mode setting signal used for selecting one of a plurality of switching modes (M1, M2, M3) each defining a timing with which the switching by the switching circuit is done. The switching control circuit (10, 26) generates the switching signal based on the state indicating signals output from the control stage circuit and the mode setting signal indicative of one of the plurality of switching modes supplied from the switching mode setting circuit.
Inventors
- 👤 Kazushi Sakamoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 12:32
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F15/8084; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3851
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
261 words
A multiprocessor control system adapted to a multiprocessor system including a plurality of first execution units (12, 13) each processing a first group of instructions, and a single second execution unit (14) processing a second group of instructions supplied from said plurality of first execution units, said second execution unit including a plurality of pipelines (150, 151, 153 - 155) used for executing said second group of instructions, characterized in that said multiprocessor control system comprises switching means (6; 25) for selectively switching said second group of instructions supplied from said first execution units to thereby select said second group of instructions relating to one of said plurality of first execution units; control stage means (4, 5, 7 - 9; 23, 24, 28 - 30) including a plurality of register stages used for controlling a pipeline process, for sequentially storing said second group of instructions relating to said selected one of said first execution units in said register stages and for outputting, for every register stage, a state indicating signal indicating state information on the corresponding register stage; switching mode setting means (11, 27) for generating a mode setting signal used for selecting one of a plurality of switching modes (M1, M2, M3) each defining a timing with which the switching by said switching means is done; and switching control means (10; 26) for generating said switching signal based on said state indicating signals output from said control stage means and said mode setting signal indicative of one of the plurality of switching modes supplied from said switching mode setting means.
Claim 2
Dependent Claim
261 words
A multiprocessor control system adapted to a multiprocessor system including a plurality of first execution units (12, 13) each processing a first group of instructions, and a single second execution unit (14) processing a second group of instructions supplied from said plurality of first execution units, said second execution unit including a plurality of pipelines (150, 151, 153 - 155) used for executing said second group of instructions, characterized in that said multiprocessor control system comprises switching means (6; 25) for selectively switching said second group of instructions supplied from said first execution units to thereby select said second group of instructions relating to one of said plurality of first execution units; control stage means (4, 5, 7 - 9; 23, 24, 28 - 30) including a plurality of register stages used for controlling a pipeline process, for sequentially storing said second group of instructions relating to said selected one of said first execution units in said register stages and for outputting, for every register stage, a state indicating signal indicating state information on the corresponding register stage; switching mode setting means (11, 27) for generating a mode setting signal used for selecting one of a plurality of switching modes (M1, M2, M3) each defining a timing with which the switching by said switching means is done; and switching control means (10; 26) for generating said switching signal based on said state indicating signals output from said control stage means and said mode setting signal indicative of one of the plurality of switching modes supplied from said switching mode setting means.
Claim 3
Dependent Claim
89 words
A multiprocessor control system as claimed in claim 1, characterized in that said plurality of register stages (4, 5, 7 - 9; 23, 24, 28 - 30) included in said control register means are cascaded, and that said plurality of switching modes (M1, M2, M3) include a first switching mode (M1) in which the switching by said switching means (6; 25) is done when all instructions relating to said second group supplied from one of said plurality of first execution units completely go out of all the register stages.
Claim 4
Dependent Claim
134 words
A multiprocessor control system as claimed in any of claims 1 and 2, characterized in that said plurality of register stages (4, 5, 7 - 9; 23, 24, 28 - 30) included in said control stage means are cascaded, and said plurality of switching modes (M1, M2, M3) include a second switching mode (M2) in which the switching by said switching means (6; 25) is done when all instructions relating to said second group supplied from one of said plurality of first execution units completely go out of last one of said cascaded register stages located at the end thereof, and said second group of instructions stored in said control stage means is supplied to one of said pipelines through last register stage (9, 30) located at the end of said cascaded register stages.
Claim 5
Dependent Claim
136 words
A multiprocessor control system as claimed in any of claims 1 to 3, characterized in that said plurality of register stages (4, 5, 7 - 9; 23, 24, 28 - 30) included in said control stage means are cascaded, and said plurality of switching modes (M1, M2, M3) include a third switching mode (M3) in which the switching by said switching means (6; 25) is done when all instructions relating to said second group supplied from one of said plurality of first execution units completely go out of at least last two (8, 9; 29; 30) of said cascaded register stages, and said second group of instructions stored in said control stage means is supplied to one of said pipelines through said last register stage (9, 30) located at the end of said cascaded cascaded stages.
Claim 6
Dependent Claim
44 words
A multiprocessor control system as claimed in any of claims 1 to 4, characterized by further comprising means (6, 25, L1, L2) for supplying a signal indicative of said timing of the switching to each of said plurality of first execution units (12, 13).
Claim 7
Dependent Claim
40 words
A multiprocessor control system as claimed in claim 5, characterized in that each of said first execution units (12, 13) comprises a timer used for recording an operation time based on said signal indicative of said timing of the switching.
Claim 8
Dependent Claim
82 words
A multiprocessor control system as claimed in any of claims 1 to 6, characterized in that said control stage means comprises, for every register stage, generating means (23-4, 28-2, 29-4, 30-5) for generating said state indicating signal for each of said plurality of first execution units (12, 13), and that said state indicating signal generated for each of the first execution units indicates whether or not at least one of said second group of instructions is stored in the corresponding register stage.
Claim 9
Dependent Claim
209 words
A multiprocessor control system as claimed in any of claims 1 to 7, characterized in that: said multiprocessor system comprises two first execution units (12, 13), said switching control means (26) comprises first busy detecting means (26-1) relating to one (12) of said two first execution units, for determining whether or not the switching mode set by said switching mode setting means (27) can be done by referring to said state indicating signal supplied from each of said register stages (4, 5, 7 - 9; 23, 24, 28 - 30) and said switching mode setting signal supplied from said switching mode setting means (27) and for generating a first busy signal (BUSY0) indicative of the determination result, and second busy detecting means (26-2) relating to the other (13) of said two first execution units, for determining whether or not the switching mode set by said switching mode setting means (27) can be done by referring to said state indicating signal supplied from each of said register stages and said mode setting signal supplied from said switching mode setting means and for generating a second busy signal (BUSY1) indicative of the determination result, and said first and second busy signals are supplied, as said switching signal, to said switching means.
Claim 10
Dependent Claim
155 words
A multiprocessor control system as claimed in claim 8, characterized in that each of said first and second busy detecting means (26-1, 26-2) comprises: a plurality of OR gates (31 - 33; 41 - 43) each performing an OR operation on said state indicating signals supplied from two or more register stages among said plurality of register stages, thereby outputting an OR operation result, a plurality of AND gates (34 - 36; 44 - 46) respectively provided for said OR gates, each performing an AND operation on said OR operation result supplied from related one of said OR gates and one of said plurality of switching modes (M1, M2, M3), thereby outputting an AND operation result, and an OR gate (37; 47) performing an OR operation on said AND operation results supplied from said plurality of AND gates, thereby outputting said first or second busy signal (BUSY0, BUSY1) to be supplied to said switching circuit.
Claim 11
Dependent Claim
102 words
A multiprocessor control system as claimed in any of claims 1 to 9, characterized in that: said multiprocessor system comprises two first execution units (12, 13), and said control stage means comprises first fetch register means (23), connected between one (12) of said first execution units and said switching means (25), for fetching said second group of instructions from said one of said first execution units, and second fetch register means (24), connected between the other (13) of said first execution units and said switching means (25), for fetching said second group of instructions from the other of said first execution means.
Claim 12
Dependent Claim
185 words
A multiprocessor control system as claimed in claim 10, characterized in that said switching means (25) comprises; first and second flip-flops (50, 51) each having set and reset terminals, first and second inverters (55, 56), first and second AND gates (52, 53), and an OR gates (54), said first busy signal (BUSY0) is supplied, through said first inverter, to the reset terminal of said first flip-flop and the set terminal of said second flip-flop, said second busy signal (BUSY1) is supplied, through said second inverter, to said set terminal of said first flip-flop and the reset terminal of said second flip-flop, outputs of said first and second flip-flops (50, 51) are supplied to said first and second AND gates (52, 53), respectively, and said first and second AND gates are supplied with said second group of instructions relating to said respective first execution units first and second stages, and outputs of said first and second AND gates are supplied to said OR gate (54), which outputs said second group of instructions related to said selected one of first execution units to said control stage means.
Claim 13
Dependent Claim
43 words
A multiprocessor control system as claimed in claim 11, characterized in that the set terminal of said first flip-flop (50) has priority over the reset terminal thereof, and the reset terminal of said second flip-flop (51) has priority over the set terminal thereof.
Claim 14
Dependent Claim
57 words
A multiprocessor control system as claimed in claim 12, characterized in that said switching means (25) further comprises third and fourth inverters (57, 58) used for inverting the outputs of said first and second flip-flops (50, 51), respectively, and inverted outputs are said signals used for controlling the timers of said related first execution units (12, 13).
Claim 15
Dependent Claim
107 words
A multiprocessor control system as claimed in any of claims 10 to 13, characterized in that each of first and second fetch register means (23; 24) comprises a register (23-1) temporarily storing the second group of instructions supplied from the corresponding first execution unit (12), a buffer (23-2) buffering the second group of instructions supplied from the corresponding first execution unit, a selector (23-3) selecting one of said register and buffer to connect the selected one of said register and buffer to said switching means, and logic means (23-4) for generating said state indicating signal (VFS0-BUSY0; VFS1-BUSY1) based on the storage contents of said register and buffer.
Claim 16
Dependent Claim
92 words
A multiprocessor control system as claimed in any of claims 1 to 14, characterized in that said control stage means comprises pre-decoding register means (28-1), connected to said switching means (25), for decoding said second group of instructions supplied from the selected one of said first execution units through said switching means to determine which one of said first execution units is associated with said supplied second group of instructions, and logic means (28-2) for generating said state indicating signal (VPS-BUSY0; VPS-BUSY1) based on the storage contents of said pre-decoding register means.
Claim 17
Dependent Claim
143 words
A multiprocessor control system as claimed in claim 15, characterized in that said control stage means comprises first queuing register means (29-1), connected to said pre-decoding means (28), for queuing said second group of instructions relating to some (150, 151) of said pipelines and supplied from said pre-decoding register means, second queuing register means (29-2), connected to said pre-decoding means, for queuing said second group of instructions relating to the rest (153 - 155) of said pipelines and supplied from said pre-decoding register means, a selector (29-3) for selecting one of said first and second queuing register means so that the second group of instructions relating to the selected one of said first and second queuing register means, and logic means (29-4) for generating said state indicating signal (VQS-BUSY0, VQS-BUSY1) based on the storage contents of said first and second queuing register means.
Claim 18
Dependent Claim
60 words
A multiprocessor control system as claimed in claim 16, characterized in that said control stage means comprises supervisory means (30-1, 30-2, 30-3, 30-4) for storing said second group of instructions to be supplied to one of said pipelines, and logic means (30-5) for generating said state indicating signal (LSR-BUSY0, LSR-BUSY1) based on the storage contents of said supervisory register means.
Claim 19
Dependent Claim
28 words
A multiprocessor control system as claimed in claim 17, characterized in that said supervisory means (30-1, 30-2, 30-3, 30-4) stores said second group of instructions for every pipeline.
Claim 20
Dependent Claim
56 words
A multiprocessor control system as claimed in any of claims 1 to 18, characterized in that said switching means (6, 25), said control stage means (4, 5, 7 - 9; 23, 24, 28 - 30), said switching mode setting means (11, 27) and said switching control means (10, 26) are provided in said second execution unit.
Claim 21
Dependent Claim
38 words
A multiprocessor control system as claimed in any of claims 1 to 19, characterized in that each of said first execution units (12, 13) is a scalar vector unit, and said second execution unit is a vector unit.
Claim 22
Dependent Claim
39 words
A multiprocessor control system as claimed in any of claims 1 to 19, characterized in that each of said first execution units (12, 13) is a small-scale execution unit, and said second execution unit is a large-scale execution unit.
References Cited (Backward Citations)
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