Patent EP0344081A2 successfully refreshed from Google Patents.
EP0344081A2
Expired / Lapsed
EP
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Bidirectional buffer with latch and parity capability
Assignee: International Business Machines Corp
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Filing: 1989-04-11
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Granted: —
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Expires: 2009-04-11
Abstract
Abstract A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of birectional bit buffer circuits. Each of the birectional bit buffer circuits includes a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.
Inventors
- 👤 Patrick Maurice Bland
- 👤 Kevin Gerrard Kramer
- 👤 Mark Edward Dean
- 👤 Susan Lynn Tempest
- 👤 Gene Joseph Gaudenzi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 09:02
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F13/4004; G06F13/4027; G06F13/405; G06F13/4059; G06F13/4063; G06F13/4068; G06F13/4072; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/0823; H03K19/0826; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
204 words
Apparatus for buffering and parity checking digital data communicated between first and second data buses, comprising a plurality of bidirectional bit buffer circuits, each of said bidirectional bit buffer circuits including, a first data path comprising a receiver having an input connected to said first data bus, a latch having an input connected to the output of said receiver, and a driver having an input connected to the output of said latch and an output connected to said second data bus, a second data path comprising a receiver having an input connected to said second data bus, a latch having an input connected to the output of said receiver, and a driver having an input connected to the output of said latch and an output connected to said first data bus, means for controlling said drivers to selectively place the output of said drivers in an active driving or high impedance state, and means for controlling said data latches to selectively latch or pass through data; and parity generating means connected at the output of said first data path latch of said bidirectional bit buffer circuits for generating a parity signal responsive to the data at the output of said first data patch latches.
Claim 2
Dependent Claim
204 words
Apparatus for buffering and parity checking digital data communicated between first and second data buses, comprising a plurality of bidirectional bit buffer circuits, each of said bidirectional bit buffer circuits including, a first data path comprising a receiver having an input connected to said first data bus, a latch having an input connected to the output of said receiver, and a driver having an input connected to the output of said latch and an output connected to said second data bus, a second data path comprising a receiver having an input connected to said second data bus, a latch having an input connected to the output of said receiver, and a driver having an input connected to the output of said latch and an output connected to said first data bus, means for controlling said drivers to selectively place the output of said drivers in an active driving or high impedance state, and means for controlling said data latches to selectively latch or pass through data; and parity generating means connected at the output of said first data path latch of said bidirectional bit buffer circuits for generating a parity signal responsive to the data at the output of said first data patch latches.
Claim 3
Dependent Claim
43 words
Apparatus in accordance with claim 1 and further including error detecting means connected to the output of said parity generating means for comparing said parity signal with a second parity and producing a error signal if the two parity signals are not identical.
Claim 4
Dependent Claim
44 words
Apparatus in accordance with claim 2 wherein said error detecting means comprises a logical exclusive-OR gate having a first input connected to the output of said parity generator; and means for applying a second parity signal to a second input of said exclusive-OR gate.
Claim 5
Dependent Claim
72 words
Apparatus in accordance with claim 3 wherein said second parity signal applying means comprises : a parity terminal for receiving said second parity signal ; a parity receiver connected at its input to said parity terminal and at its output to said second input of said exclusive-OR gate; and a parity driver having an input connected to the output of said parity generating means and an output connected to said parity terminal.
Claim 6
Dependent Claim
40 words
Apparatus in accordance with claim 4 wherein said second parity signal applying means further comprises a control receiver having an output connected both to the control terminal of said parity driver and to the enable terminal of said exclusive-OR gate.
Claim 7
Dependent Claim
55 words
Apparatus in accordance with claim 1 wherein : in each of said bit buffer circuits, each of said latches is connected in a T-connection with its corresponding receiver and driver at a circuit node; and each of said drivers includes a phase splitting circuit connected to its corresponding receiver and latch at said circuit node.
Claim 8
Dependent Claim
122 words
In a circuit of the type including means connected to a circuit node for applying a data signal to said circuit node, and means connected to said circuit node for sensing said data signal, a transparent latch circuit responsive to a logical control signal for holding said data signal at said circuit node, said transparent latch circuit comprising: latch means connected to said circuit node in a T-connection with said data applying and sensing means for selectively holding said data signal at said circuit note; and actuating means connected to said latch means for actuating said latch means to pass through said data signal or hold said data signal at said circuit node regardless of the state of said data applying means.
Claim 9
Dependent Claim
122 words
In a circuit of the type including means connected to a circuit node for applying a data signal to said circuit node, and means connected to said circuit node for sensing said data signal, a transparent latch circuit responsive to a logical control signal for holding said data signal at said circuit node, said transparent latch circuit comprising: latch means connected to said circuit node in a T-connection with said data applying and sensing means for selectively holding said data signal at said circuit note; and actuating means connected to said latch means for actuating said latch means to pass through said data signal or hold said data signal at said circuit node regardless of the state of said data applying means.
Claim 10
Dependent Claim
164 words
A transparent latch circuit responsive to a logical control signal for holding a data signal applied by an input circuit at a circuit node, comprising : a first transistor for providing current from a first terminal to a second terminal in accordance with a signal applied at a control terminal thereof, said first transistor having its first terminal connected to said circuit node and its second terminal connected to a reference potential; means for applying said control signal to the control terminal of said first transistor; a second transistor having its first terminal connected to the control terminal of said first transistor and its second terminal connected to said reference potential; a resistor connected intermediate said circuit node and the control terminal of said second transistor; and means responsive to said logical control signal for generating a second control signal operative to isolate said circuit node from said input circuit when said latch is activated to hold said data signal at said circuit node.
Claim 11
Dependent Claim
164 words
A transparent latch circuit responsive to a logical control signal for holding a data signal applied by an input circuit at a circuit node, comprising : a first transistor for providing current from a first terminal to a second terminal in accordance with a signal applied at a control terminal thereof, said first transistor having its first terminal connected to said circuit node and its second terminal connected to a reference potential; means for applying said control signal to the control terminal of said first transistor; a second transistor having its first terminal connected to the control terminal of said first transistor and its second terminal connected to said reference potential; a resistor connected intermediate said circuit node and the control terminal of said second transistor; and means responsive to said logical control signal for generating a second control signal operative to isolate said circuit node from said input circuit when said latch is activated to hold said data signal at said circuit node.
Claim 12
Dependent Claim
59 words
A transparent latch circuit in accordance with claim 8 wherein said generating means comprises : a third transistor; means for applying said control signal to the control terminal of said third transistor; and the second terminal of said third transistor connected to a second reference potential; said second control signal generated at the first terminal of said third transistor.
Claim 13
Dependent Claim
176 words
In a driver circuit of the type responsive to a logical input signal applied to an input terminal for actuating first or second driving means, said first driving means actuable to provide a logical high signal level at an output terminal, said second driving means actuable to provide a logical low signal level at said output terminal, a phase splitter circuit comprising : a first transistor for providing current from a first terminal to a second terminal in accordance with a signal applied at a control terminal thereof, said first transistor having its control terminal connected to said input terminal and its second terminal connected to a reference potential; means for applying a supply voltage to the first terminal of said first transistor; the first terminal of said first transistor connected to said first driving means; a second transistor having its second terminal connected to said input terminal; means for applying said supply voltage to the control terminal of said second transistor; and the first terminal of said second transistor connected to said second driving means.
Claim 14
Dependent Claim
176 words
In a driver circuit of the type responsive to a logical input signal applied to an input terminal for actuating first or second driving means, said first driving means actuable to provide a logical high signal level at an output terminal, said second driving means actuable to provide a logical low signal level at said output terminal, a phase splitter circuit comprising : a first transistor for providing current from a first terminal to a second terminal in accordance with a signal applied at a control terminal thereof, said first transistor having its control terminal connected to said input terminal and its second terminal connected to a reference potential; means for applying a supply voltage to the first terminal of said first transistor; the first terminal of said first transistor connected to said first driving means; a second transistor having its second terminal connected to said input terminal; means for applying said supply voltage to the control terminal of said second transistor; and the first terminal of said second transistor connected to said second driving means.
Claim 15
Dependent Claim
62 words
A phase splitter circuit in accordance with claim 10 wherein : said first driving means includes a third transistor; said second driving means includes a fourth transistor; the first terminal of said first transistor is connected to the control terminal of said third transistor; and the first terminal of said second transistor is connected to the control terminal of said fourth transistor.
Claim 16
Dependent Claim
39 words
A phase splitter circuit in accordance with claim 11 and further comprising : a first Schottky diode connected across the base-collector junction of said first transistor; and a second Schottky diode connected across the base-collector junction of said transistor.
References Cited (Backward Citations)
No citation records indexed.
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