Patent EP0343988A2 successfully refreshed from Google Patents.
EP0343988A2
Expired / Lapsed
EP
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Data processing apparatus with selective instruction prefetching
Assignee: International Business Machines Corp
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Filing: 1989-05-25
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Granted: —
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Expires: 2009-05-25
Abstract
Abstract In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.
Inventors
- 👤 Ralph Murray Begun
- 👤 Patrick Maurice Bland
- 👤 Mark Edward Dean
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 15:53
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0888; G06F5/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
142 words
Data processing apparatus comprising an instruction execution unit of a given bit width, an asynchronous next address generating means capable of generating, when enabled, the address of the next instruction required by the instruction execution unit during execution of the instruction currently executing, whereby instructions can be prefetched, means for interfacing the execution unit with addressable system components of the same and/or smaller bit widths, the system component addresses within a certain specified range of system component addresses relating exclusively to components of the same bit width as that of the execution unit, means for generating a next address signal as a function of the execution of the instruction currently executing to enable the next address generating means and means for preventing a next address signal becoming available during execution of an instruction relating to an address outside the specified address range.
Claim 2
Dependent Claim
142 words
Data processing apparatus comprising an instruction execution unit of a given bit width, an asynchronous next address generating means capable of generating, when enabled, the address of the next instruction required by the instruction execution unit during execution of the instruction currently executing, whereby instructions can be prefetched, means for interfacing the execution unit with addressable system components of the same and/or smaller bit widths, the system component addresses within a certain specified range of system component addresses relating exclusively to components of the same bit width as that of the execution unit, means for generating a next address signal as a function of the execution of the instruction currently executing to enable the next address generating means and means for preventing a next address signal becoming available during execution of an instruction relating to an address outside the specified address range.
Claim 3
Dependent Claim
102 words
Apparatus as claimed in claim 1, wherein the instruction execution unit and the address generating means are two units within a microprocessor, the microprocessor being connected to a cache memory subsystem, including a cache controller and a cache memory of the given bit width, by a local bus of the given bit width which also interfaces with a system bus connecting to the addressable system components, the cache memory subsystem caching data with respect to only those system components within the specified range of addresses, the next address signal generating means being connected between the cache controller and the address generating means.
Claim 4
Dependent Claim
58 words
Apparatus as claimed in claim 2, wherein the next address signal generating means, absent any action by the preventing means, is enabled by a signal from the cache controller indicating that there is no valid address on the local bus and by a signal from the system indicating that a next address is required from the local bus.
Claim 5
Dependent Claim
55 words
Apparatus as claimed in claim 3, wherein the preventing means includes an address decoder connected to the address lines of the local bus for determining whether or not an address thereon lies within the specified range and, in response to an out-of-range determination, to generate a signal to disable the next address signal generating means.
Claim 6
Dependent Claim
52 words
Apparatus as claimed in claim 4, wherein the preventing means is also responsive to a system generated signal indicating that the address indicated on the local bus is not cacheable - even though it lies within the specified range - to generate a signal to disable the next address signal generating means.
Claim 7
Dependent Claim
67 words
Apparatus as claimed in claim 5, wherein the microprocessor is responsive to a signal indicating that an addressed system component is of half the bit width of the microprocessor for programming a double execution cycle, logic being provided, responsive to signal combinations indicating that an addressed system component is a quarter of the bit width of the microprocessor, to re-double the execution cycle, transparantly to the microprocessor.
Claim 8
Independent Claim
157 words
A method of operating a data processing system which comprises an instruction execution unit of a given bit width, an asynchronous next address generating means capable of generating, when enabled, the address of the next instruction required by the instruction execution unit during execution of the instruction currently executing, whereby instructions can be prefetched, and means for interfacing the execution unit with addressable system components of the same and/or smaller bit widths, the method comprising assigning system component addresses within a certain specified range thereof exclusively to components of the same bit width as that of the execution unit, generating a control signal if execution of an instruction relating to an address outside the specified address range is detected, and in response to such a control signal inhibiting generation of a next address signal as a function of the execution of the instruction currently executing to prevent early generation of the next address and hence instruction prefetching.
Claim 9
Independent Claim
157 words
A method of operating a data processing system which comprises an instruction execution unit of a given bit width, an asynchronous next address generating means capable of generating, when enabled, the address of the next instruction required by the instruction execution unit during execution of the instruction currently executing, whereby instructions can be prefetched, and means for interfacing the execution unit with addressable system components of the same and/or smaller bit widths, the method comprising assigning system component addresses within a certain specified range thereof exclusively to components of the same bit width as that of the execution unit, generating a control signal if execution of an instruction relating to an address outside the specified address range is detected, and in response to such a control signal inhibiting generation of a next address signal as a function of the execution of the instruction currently executing to prevent early generation of the next address and hence instruction prefetching.
References Cited (Backward Citations)
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