Patent EP0343968A2 successfully refreshed from Google Patents.
EP0343968A2
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EP
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Programmable logic device
Assignee: Fujitsu VLSI Ltd
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Filing: 1989-05-24
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Granted: —
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Expires: 2009-05-24
Abstract
Abstract A programmable logic device includes: a programmable AND array (14); an OR array (17) operatively connected to the AND array; a plurality of external terminals (I/O1 SIMILAR I/On); and a plurality of cell blocks (121 SIMILAR 12n) operatively connected to the AND array and OR array and provided for each of the plurality of external terminals, each receiving two output signals (OR1,OR2) from the OR array and outputting a signal to a corresponding external terminal based on the two output signals. By controlling an input/output of an input signal and an internally produced signal and a feedback thereof to the AND array, it is possible to realize various logic constitutions and develop a degree of freedom of the logic design in the entire device.
Inventors
- 👤 Mitsuo Higuchi
- 👤 Kiyonori Ogura
- 👤 Kohji Shimbayashi
- 👤 Yasuhiro Nakaoka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 19:44
CPC Classifications
H; H03; H03K; H03K19/00; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/693; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
94 words
A programmable logic device comprising: a programmable AND array (14, 16); an OR array (17, 18) operatively connected to said AND array; a plurality of external terminals (I/0₁-I/0 n ); and a plurality of cell blocks (12₁-12 n ) operatively connected to the AND array and OR array and provided for each of the plurality of external terminals, characterised in that each of the cell blocks (12₁-12 n ) receives two output signals (OR1, OR2) from the OR array and outputs a signal to a corresponding external terminal based on the two output signals.
Claim 2
Dependent Claim
94 words
A programmable logic device comprising: a programmable AND array (14, 16); an OR array (17, 18) operatively connected to said AND array; a plurality of external terminals (I/0₁-I/0 n ); and a plurality of cell blocks (12₁-12 n ) operatively connected to the AND array and OR array and provided for each of the plurality of external terminals, characterised in that each of the cell blocks (12₁-12 n ) receives two output signals (OR1, OR2) from the OR array and outputs a signal to a corresponding external terminal based on the two output signals.
Claim 3
Dependent Claim
180 words
A device as set forth in claim 1, wherein each of said plurality of cell blocks further receives an output enable control signal (OE) from said OR array and includes: a programmable register circuit (20A,20B) responsive to first and second clock signals (CLKA, CLKB), latching two output signals fed from said OR array and an input signal fed from an external of said device; a switch circuit (21-28, 31-33) having a plurality of programmable switches operatively connected to said programmable register circuit, switching connections of said switches in accordance with the contents stored in a programmable non-volatile memory means (19) and determining the status of said programmable register circuit; and an input/output control circuit (29,30,36,37) responsive to said output enable control signal from said OR array, switching an output of a signal internally produced based on the switching of said switch circuit and an input of said input signal from the external, whereby the input/output of said input signal and said internally produced signal and a feedback thereof to said AND array are controlled to attain a desired logic constitution.
Claim 4
Dependent Claim
66 words
A device as set forth in claim 2, further comprising an exclusively-OR gate (34) responsive to two output signals (OR1, OR2) fed from said OR array, wherein an output signal (XOR) of said exclusively-OR gate is latched in said programmable register circuit based on the switching of said switch circuit, and fed back to said AND array or output externally according to said desired logic consitution.
Claim 5
Dependent Claim
92 words
A device as set forth in claim 3, wherein said programmable register circuit comprises a first programmable flip-flop circuit (20A) latching one (OR1) of two output signals fed from said OR array or the output signal (XOR) of said exclusively-OR gate in response to said first clock signal (CLKA) and a second programmable flip-flop circuit (20B) latching another (OR2) of two output signals fed from said OR array, the output signal (XOR) of said exclusively-OR gate or the input signal fed from the external in response to said second clock signal (CLKB).
Claim 6
Dependent Claim
69 words
A device as set forth in claim 4, wherein each of said first and second programmable flip-flop circuits (20A,20B) comprises a JK-type flip-flop (20a) and a plurality of programmable switches (20b,20c) operatively connected to said JK-type flip-flop, and switches connections of said switches in accordance with the contents stored in said programmable non-volatile memory means to constitute one of a JK-type flip-flop, a D-type flip-flop and a T-type flip-flop.
Claim 7
Dependent Claim
66 words
A device as set forth in claim 4, wherein said input/output control circuit comprises a D-type flip-flop (30) latching the output enable control signal (OE) fed from said OR array in response to said first clock signal (CLKA) and selects the output signal of said D-type flip-flop or said output enable control signal to control the input/output of said input signal and said internally produced signal.
Claim 8
Independent Claim
39 words
A device as set forth in any one of claims 2 to 6, wherein the contents stored in said programmable non-volatile memory means (19) constitute a plurality of control signals for switching connections of said plurality of programmable switches.
Claim 9
Dependent Claim
106 words
A device as set forth in claim 7, wherein said switch circuit includes a programmable switch (27) selecting one (OR1) of two output signals fed from said OR array or the output signal (XOR) of said exclusively-OR gate in response to a control signal (C7) and feeding the selected signal to said first flip-flop circuit (20A), and a programmable switch (31) selecting another (OR2) of two output signals fed from said OR array, the output signal (XOR) of said exclusively-OR gate or the input signal fed in externally in response to another control signal (C11,C12) and feeding the selected signal to said second flip-flop circuit (20B).
Claim 10
Dependent Claim
91 words
A device as set forth in claim 7, wherein said switch circuit includes a first programmable switch (32) selecting one (OR1) of two output signals fed from said OR array, the output signal (XOR) of said exclusively-OR gate or the output signal (Q1) of said first flip-flop circuit in response to a control signal (C21,C22), and a second programmable switch (28) selecting the signal selected by said first programmable switch or the inverted signal in response to another control signal (C8) and outputting the selected signal to said input/output control circuit.
Claim 11
Dependent Claim
62 words
A device as set forth in claim 7, wherein said switch circuit includes a programmable switch (33) responsive to a control signal (C31∼C33), selecting one of two output signals (OR1,OR2) fed from said OR array, the output signals (Q1,Q2) of said first and second flip-flop circuits, the output signal (XOR) of said exclusively-OR gate and the input signal fed from the external.
Claim 12
Dependent Claim
58 words
A device as set forth in claim 7, wherein said switch circuit includes a pair of programmable switches (21,22), each selecting one of two different external clock signals (CLK1,CLK2) in response to a control signal (C1,C2), a pair of clock signals (CLKA,CLKB) selected by said pair of programmable switches being used as said first and second clock signals.
Claim 13
Dependent Claim
53 words
A device as set forth in claim 7, wherein said switch circuit includes a pair of programmable switches (23,24), each selecting a feeding or a prohibition of said feeding of a set signal (SETA,SETB) for bringing the corresponding programmable flip-flop circuit (20A,20B) to the set state in response to a control signal (C3,C4).
Claim 14
Dependent Claim
53 words
A device as set forth in claim 7, wherein said switch circuit includes a pair of programmable switches (25,26), each selecting a feeding or a prohibition of said feeding of a clear signal (CLRA,CLRB) for bringing the corresponding programmable flip-flop circuit (20A,20B) to the reset state in response to a control signal (C5,C6).
References Cited (Backward Citations)
No citation records indexed.
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