Patent EP0343770A2 successfully refreshed from Google Patents.
EP0343770A2
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EP
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Multi-bus microcomputer system with bus arbitration
Assignee: International Business Machines Corp
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Filing: 1989-03-03
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Granted: —
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Expires: 2009-03-03
Abstract
Abstract A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.
Inventors
- 👤 Ralph Murray Begun
- 👤 Patrick Maurice Bland
- 👤 Mark Edward Dean
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 23:13
CPC Classifications
G; G06; G06F; G06F8/00; G06F8/70; G06F8/71; G02; G02B; G02B27/00; G02B27/28; G03; G03B; G03B21/00; G03B21/54; G03B21/56; G03B21/60; G03B21/604; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F8/20
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
155 words
A multi-bus microcomputer system comprising a processor and a cache subsystem connected together by a CPU local bus, a random access memory, an arbitration supervisor and a plurality of other functional units connected together by a system bus, means coupling said CPU local bus and said system bus, both said CPU local bus and said system bus including a plurality of conductors dedicated to arbitrating access to said system bus by at least some of said plurality of other functional units, one of said plurality of said conductors providing a preempt signal, and a preempt signal source with inputs responsive to a CPU local bus cycle extending beyond a minimum duration, said preempt signal source having an output coupled to said CPU local bus for asserting a preempt signal effective at any functional unit with access to said system bus for limiting a duration of said access in response to receipt of said preempt signal.
Claim 2
Dependent Claim
155 words
A multi-bus microcomputer system comprising a processor and a cache subsystem connected together by a CPU local bus, a random access memory, an arbitration supervisor and a plurality of other functional units connected together by a system bus, means coupling said CPU local bus and said system bus, both said CPU local bus and said system bus including a plurality of conductors dedicated to arbitrating access to said system bus by at least some of said plurality of other functional units, one of said plurality of said conductors providing a preempt signal, and a preempt signal source with inputs responsive to a CPU local bus cycle extending beyond a minimum duration, said preempt signal source having an output coupled to said CPU local bus for asserting a preempt signal effective at any functional unit with access to said system bus for limiting a duration of said access in response to receipt of said preempt signal.
Claim 3
Dependent Claim
65 words
A multi-bus microcomputer system according to claim 1 including an arbitration supervisor comprising a source of an arbitration grant signal, means responsive to said preempt signal to prepare for an arbitration phase, means for initiating an arbitration phase in response to a signal representing termination of a current bus users use of the bus, and means for signaling a new arbitration phase to said processor.
Claim 4
Dependent Claim
36 words
A multi-bus microcomputer system according to claim 2 wherein said processor responds to said signaling from said arbitration supervisor representing a new arbitration phase while said preempt signal is asserted to immediately access said system bus.
Claim 5
Dependent Claim
55 words
A multi-bus microcomputer system according to any one of the previous claims wherein said preempt signal source is further responsive to a programmable signal to, allow production of said preempt signal in one state of said programmable signal and to inhibit production of said preempt signal when said programmable signal is in a further state.
Claim 6
Dependent Claim
74 words
A multi-bus microcomputer system according to any one of the previous claims, further including an optional feature bus coupled through said system bus and said means for coupling to said CPU local bus, whereby devices coupled to said optional feature bus may arbitrate for access to said system bus and are responsive to said preempt signal from said preempt signal source to terminate a bus access in response to receipt of said preempt signal.
Claim 7
Dependent Claim
84 words
A multi-bus microcomputer system according to claim 1 in which said plurality of conductors include an arbitration grant conductor carrying an arbitration grant signal to establish an arbitration phase for arbitration of access among a plurality of devices when said signal is in one state and a grant phase for use of the system bus by that device winning said arbitration phase, and wherein said CPU includes means for accessing said system bus in that arbitration phase immediately following assertion of said preempt signal.
References Cited (Backward Citations)
No citation records indexed.
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