High performance interconnect system for an integrated circuit

Claim 1

A method of fabricating a high performance interconnect structure for electrically connecting regions in a semiconductor substrate, said method comprising the steps of: (a) forming a first dielectric layer on said substrate; (b) forming contact holes in said first dielectric layer in predetermined spaced relation with said regions to expose contact areas thereon; (c) forming a first metal layer over said first dielectric layer and into said contact holes, making contact with said contact areas; (d) forming a first level of interconnects in said first metal layer; (e) forming a second dielectric layer, having a substantially planar upper surface, over said first level of interconnects; (f) forming at least one via opening in said second dielectric layer in predetermined spaced relation with said underlying first level of interconnects; (g) forming a second metal layer over said second dielectric layer and into said via openings, making contact with said exposed regions of said first level of interconnects; (h) patterning said second metal layer into a second level of interconnects; (i) removing said second dielectric layer leaving gaps between adjacent interconnects of the second interconnect level and between interconnects of the first and second interconnect levels; and (j) forming a solid dielectric layer around the interconnects of the second interconnect level without filling in said gaps.