Patent EP0342736A1 successfully refreshed from Google Patents.
EP0342736A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Phase-locked-loop cicuit and bit-detection arrangement comprising such a phase-locked-loop circuit
Assignee: Koninklijke Philips NV
•
Filing: 1989-05-10
•
Granted: —
•
Expires: 2009-05-10
Abstract
Abstract A digital phase-locked-loop circuit is revealed for deriving from a sequence of samples (J₁, ... J₂₀) of a band-limited data signal (Vt) the phase of the data signal at the sampling instants. The circuit comprises a discrete-time oscillator 10 for generating a sequence of phase values (F₁, ... F₂₀) which characterise a periodic signal (Vkl) which varies as a linear function of time between two constant limit values (E, -E). The frequency of the signal (Vk1) characterized by the phase value is proportional to a control value (I). An interpolation circuit (2) derives from the sampes (J₁, ... J₂₀) the relative positions (tf/T) occupied by the detection-level crossings of the data signal (Vt) relative to the sampling instants. A phase detector (3) derives the difference (ΔF) between the actual phase of the data signal (Vt) and the phase as indicated by the phase values (F) from said relative positions (tf/T) and the phase values (F). By means of a digital sequential filter (9) the discrete-time oscillator (10) is controlled in such a way that said phase difference remains substantially zero. Moreover, a bit-detection arrangement comprising the phase-locked-loop circuit is revealed.
Inventors
- 👤 Antonia Cornelia Van Rens
- 👤 Eise Carel Dijkmans
- 👤 Edward Ferdinand Stikvoort
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 23:55
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/099; H03L7/0991; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0334; G11B20/14; G11B20/1403; H03L2207/00; H03L2207/50
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
230 words
A phase-locked-loop circuit for deriving from a sequence of samples of a band-limited data signal the phase of the data signal at the corresponding sampling instants, which circuit comprises signal-generating means for generating in synchronism with the samples a sequence of phase values characterizing a periodic signal which varies as a substantially linear function of time between two constant limit values with a frequency which proportional to a control value, means for deriving interpolation values from the samples by interpolation, which interpolation values indicate the relative positions with respect to the sampling instants of the instants at which the data signal crosses a detection-level, phase-comparison means for deriving from the phase values and the interpolation values a difference value which is indicative of the difference between the phase represented by the phase value and the actual phase of the data signal, and control means for controlling the signal-generating means depending on the difference value in such a way that the phase indicated by the phase value is maintained substantially equal to the actual phase of the data signal, characterized in that the phase-comparison means are adapted to determine a linear combination of the phase value and the product of the interpolation value and the control value in order to derive the difference value, the control means being constructed to adapt the control value depending on the linear combination thus determined.
Claim 2
Dependent Claim
230 words
A phase-locked-loop circuit for deriving from a sequence of samples of a band-limited data signal the phase of the data signal at the corresponding sampling instants, which circuit comprises signal-generating means for generating in synchronism with the samples a sequence of phase values characterizing a periodic signal which varies as a substantially linear function of time between two constant limit values with a frequency which proportional to a control value, means for deriving interpolation values from the samples by interpolation, which interpolation values indicate the relative positions with respect to the sampling instants of the instants at which the data signal crosses a detection-level, phase-comparison means for deriving from the phase values and the interpolation values a difference value which is indicative of the difference between the phase represented by the phase value and the actual phase of the data signal, and control means for controlling the signal-generating means depending on the difference value in such a way that the phase indicated by the phase value is maintained substantially equal to the actual phase of the data signal, characterized in that the phase-comparison means are adapted to determine a linear combination of the phase value and the product of the interpolation value and the control value in order to derive the difference value, the control means being constructed to adapt the control value depending on the linear combination thus determined.
Claim 3
Dependent Claim
47 words
A circuit as claimed in Claim 1, characterized in that for determing the correction value the phase-comparison means comprise a multiplier for multiplying the control value by the interpolation value and an adder circuit for determining the linear combination of the multiplication result and the phase value.
Claim 4
Dependent Claim
30 words
A circuit as claimed in Claim 1, characterized in that adapting the control value the control means comprise a sequential filter which is controlled in synchronism with the sampling-clock signal.
Claim 5
Dependent Claim
57 words
A circuit as claimed in any one of the preceding Claims, characterized in that the control means comprise means for limiting the control value to values situated between a third and a fourth limit value, which limit values respectively correspond to a minimum and a maximum permissible frequency of the periodic signal characterized by the phase values.
Claim 6
Dependent Claim
84 words
A circuit as claimed in any one of the Claims 1 to 4, characterized in that the circuit comprises a correction circuit for correcting the difference value ΔF, the relationship f between the corrected difference value ΔF* and the original difference value substantially complying with: n-1 Σ f(2π k/N + ΔF) = 0 k=1 en k-1 Σ f′(2π k/N + ΔF) = 0 k=0 where k and N are integers and where f′ is the derivative of the relationship f with respect to ΔF.
Claim 7
Dependent Claim
16 words
A circuit as claimed in Claim 5, characterized in that the relationship is a sine function.
Claim 8
Dependent Claim
30 words
A circuit as claimed in Claim 5 or 6, characterized in that the correction circuit comprises a digital memory in which the relationship f is stored as a look-up table.
Claim 9
Dependent Claim
55 words
A bit-detection arrangement for converting the sequence of samples into a binary signal made up of bit cells, which bit-detection arrangement comprises a circuit as claimed in any one of the preceding Claims and a circuit for deriving the logic values of the bit cells from the values of the samples and the phase values.
Claim 10
Dependent Claim
85 words
A bit-detection circuit as claimed in Claim 8, characterized in that the signal-generating means comprise a digital summing circuit for adapting an n-bit sum value by means of the reference value in synchronism with the sampling-clock signal, the n-1 least significant bits representing the phase values, and the bit-detection arrangement comprising means responsive to a change in logic value of the most significant bit of the sum value to generate a clock pulse of a bit-clock signal which is in synchronism with the binary signal.
Claim 11
Dependent Claim
81 words
A bit-detection arrangement as claimed in Claim 9, characterized in that the bit-detection arrangement comprises means for deriving the logic values of the bit cells from the signs of the samples at the instants at which the clock pulses of the bit-clock signal are generated and means for comparing the phase value generated immediately after the detection-level crossing with the difference value and means for inverting the logic value of the associated bit cell depending on the result of the comparion.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.