AGC delay on an integrated circuit

Claim 2

A circuit for providing a first AGC signal to a first amplifier and a different, second AGC signal to a second amplifier, said first and second amplifiers being cascaded in a radio receiver, the circuit comprising: amplitude detector means for producing on first and second conductors a differential signal related to the amplitude of signal output from said cascaded amplifiers; first, second and third transistors, each of said transistors having an input terminal, an output terminal and a bias terminal; said first and third transistors each having their input terminal coupled to said first conductor from the amplitude detector means; second transistors having its input terminal coupled to said second conductor from the amplitude detector means; the output terminals of the first and second transistors providing the first AGC signal; the output terminals of the second and third transistors providing the second AGC signal; and in which the ratio of saturation currents between the first and second transistors does not equal the ratio of saturation currents between the second and third transistors.

Claim 3

A circuit for providing a first AGC signal to a first amplifier and a different, second AGC signal to a second amplifier, said first and second amplifiers being cascaded in a radio receiver, the circuit comprising: amplitude detector means for producing on first and second conductors a differential signal related to the amplitude of signal output from said cascaded amplifiers; first and second control stages, each of said control stages comprising first and second transistors in differential configuration, each of said transistors having an input terminal, an output terminal and a bias terminal; each of said first transistors having their input terminal coupled to said first conductor from the amplitude detector means; each of said second transistors having their input terminal coupled to said second conductor from the amplitude detector means; the output terminals of the transistors in said first control stage providing the first AGC signal; the output terminals of the transistors in said second control stage providing the second AGC signal; and in which the ratio of saturation currents between the first and second transistors in the first control stage does not equal the ratio of saturation currents between the first and second transistors in the second control stage.

Claim 4

A circuit for providing a first AGC signal to a first amplifier and a different, second AGC signal to a second amplifier, said first and second amplifiers being cascaded in a radio receiver, the circuit comprising: amplitude detector means for producing on first and second conductors a differential signal related to the amplitude of signal output from said cascaded amplifiers; first and second control stages, each of said control stages comprising first and second transistors in differential configuration, each of said transistors having an input terminal, an output terminal and a bias terminal; each of said first transistors having their input terminal coupled to said first conductor from the amplitude detector means; each of said second transistors having their input terminal coupled to said second conductor from the amplitude detector means; the output terminals of the transistors in said first control stage providing the first AGC signal; the output terminals of the transistors in said second control stage providing the second AGC signal; and in which the ratio of saturation currents between the first and second transistors in the first control stage does not equal the ratio of saturation currents between the first and second transistors in the second control stage.

Claim 5

The circuit of claim 2 in which: the first control stage includes first and second load elements interposed between a power supply line and the output terminals of the first and second transistors; a third load element is interposed between the bias terminals of said first and second transistors; and in which the rate at which the first AGC signal changes as a function of changes in the differential signal provided from the amplitude detector means is set by the ratios between the impedances of the first and second load elements to the impedance of the third load element.

Claim 6

The circuit of claim 2 in which said first and second control stages are fabricated in integrated circuit form on a common substrate and in which said transistors are of different areas to achieve the difference in saturation current ratios.

Claim 7

An FM receiver incorporating the circuit of claim 4.

Claim 8

A circuit for producing an AGC signal for application to a gain-controlled amplifier in a radio receiver comprising: differential control stage means having first and second transistors in a differential configuration, the inputs of said transistors receiving a differential input signal related to the amplitude of the signal being received by the receiver, and the outputs of said transistors providing a differential AGC output signal for application to the gain-controlled amplifier, said first and second transistors having different saturation currents to yield a zero volt output signal when a certain non-zero volt differential signal is applied to their inputs.

Claim 9

A circuit for producing an AGC signal for application to a gain-controlled amplifier in a radio receiver comprising: differential control stage means having first and second transistors in a differential configuration, the inputs of said transistors receiving a differential input signal related to the amplitude of the signal being received by the receiver, and the outputs of said transistors providing a differential AGC output signal for application to the gain-controlled amplifier, said first and second transistors having different saturation currents to yield a zero volt output signal when a certain non-zero volt differential signal is applied to their inputs.

Claim 10

The circuit of claim 6 in which the first and second transistors are fabricated in integrated circuit form on a common substrate and in which the areas of said transistors are different to achieve the different saturation currents.

Claim 11

A circuit according to claim 6 in which said inputs are the bases of said transistors and in which said outputs are the collectors.

Claim 12

The circuit of claim 6 which further includes means for establishing the rate at which the differential AGC output signal changes as a function of changes in the differential input signal.

Claim 13

A circuit for staggering the generation of a second gain-reducing signal from a first gain-­reducing signal comprising: differential control stage means having first and second transistors in a differential configuration, the bases of said transistors being driven by the first gain-reducing signal and the outputs of said transistors providing the second gain-­reducing signal, the staggering of said signals being set by the area ratios of the first and second transistors.

Claim 14

A circuit for staggering the generation of a second gain-reducing signal from a first gain-­reducing signal comprising: differential control stage means having first and second transistors in a differential configuration, the bases of said transistors being driven by the first gain-reducing signal and the outputs of said transistors providing the second gain-­reducing signal, the staggering of said signals being set by the area ratios of the first and second transistors.

Claim 15

The circuit of claim 10 in which the second gain-reducing signal is ineffective in achieving substantial gain reduction until the first gain-reducing signal exceeds a value defined by the equation: V T ln(A) where V T is a thermal voltage constant and A is the ratio in areas between the first and second transistors in the differential control stage means.

Claim 16

In a method of controlling the gains of first and second amplifiers in a radio receiver, an improvement permitting the onset of significant gain reduction in the first amplifier to be staggered from the onset of significant gain reduction in the second amplifier as a function of received signal strength, comprising the steps: providing first and second AGC circuits for providing AGC signals to said first and second amplifiers, said AGC circuits having a plurality of components and having identical topologies, said circuits both being driven from a common signal source; and fabricating said circuits in integrated circuit form on a common substrate with the area of one component in the first AGC circuit being fabricated to have a desired non-unity area ratio relationship with the same component in the second AGC circuit, said non-unity area ratio effecting the staggering of the onset of significant gain reduction in the first amplifier from the onset of significant gain reduction in the second amplifier as a function of the received signal strength.

Claim 17

In a method of controlling the gains of first and second amplifiers in a radio receiver, an improvement permitting the onset of significant gain reduction in the first amplifier to be staggered from the onset of significant gain reduction in the second amplifier as a function of received signal strength, comprising the steps: providing first and second AGC circuits for providing AGC signals to said first and second amplifiers, said AGC circuits having a plurality of components and having identical topologies, said circuits both being driven from a common signal source; and fabricating said circuits in integrated circuit form on a common substrate with the area of one component in the first AGC circuit being fabricated to have a desired non-unity area ratio relationship with the same component in the second AGC circuit, said non-unity area ratio effecting the staggering of the onset of significant gain reduction in the first amplifier from the onset of significant gain reduction in the second amplifier as a function of the received signal strength.