Patent EP0342590A2 successfully refreshed from Google Patents.
EP0342590A2
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EP
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Master slice type semiconductor integrated circuit
Assignee: Toshiba Corp
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Filing: 1989-05-16
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Granted: —
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Expires: 2009-05-16
Abstract
Abstract An internal logic block (12) is arranged in a chip body (11), and I/O cells (13) and pads (14) are arranged in a peripheral portion of the chip body. Three I/O cells (13) are arranged for each pad.
Inventors
- 👤 Yasunori Intellectual Property Division Tanaka
- 👤 Teruo Intellectual Property Division Kobayashi
- 👤 Masahiro Intellectual Property Division Ishibashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 20:17
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W72/00; H10W72/90; H10W72/931; H10W72/932
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
84 words
A master slice type semiconductor integrated circuit comprising: a plurality of pads (14, 14a - 14d) arranged at a predetermined pitch; and n ( n is an integer of 2 or more) I/O cells (13, 13a - 13i) arranged for each of said plurality of pads, each I/O cell being provided with at least a buffer (15), characterized in that the n number of I/O cells (13, 13a - 13i) per pad (14, 14a - 14d) is set in accordance with the pad pitch.
Claim 2
Dependent Claim
84 words
A master slice type semiconductor integrated circuit comprising: a plurality of pads (14, 14a - 14d) arranged at a predetermined pitch; and n ( n is an integer of 2 or more) I/O cells (13, 13a - 13i) arranged for each of said plurality of pads, each I/O cell being provided with at least a buffer (15), characterized in that the n number of I/O cells (13, 13a - 13i) per pad (14, 14a - 14d) is set in accordance with the pad pitch.
Claim 3
Dependent Claim
25 words
A circuit according to claim 1, characterized in that said buffers (15) included in said I/O cells (13, 13a - 13i) have equal drive capacities.
Claim 4
Dependent Claim
29 words
A circuit according to claim 1, characterized in that each of said I/O cells (13, 13a - 13i) includes an input protective resistor (32) in addition to said buffer.
Claim 5
Dependent Claim
58 words
A master slice type semiconductor integrated circuit, comprising: a plurality of pads (14, 14a - 14d) arranged at a predetermined pitch; and I/O cells (13, 13a - 13i), the number of which is an m ( m is an integer of 2 or more) multiple of pads, each I/O cell being provided with at least a buffer (15).
Claim 6
Dependent Claim
58 words
A master slice type semiconductor integrated circuit, comprising: a plurality of pads (14, 14a - 14d) arranged at a predetermined pitch; and I/O cells (13, 13a - 13i), the number of which is an m ( m is an integer of 2 or more) multiple of pads, each I/O cell being provided with at least a buffer (15).
Claim 7
Dependent Claim
25 words
A circuit according to claim 4, characterized in that said buffers (15) included in said I/O cells (13, 13a - 13i) have equal drive capacities.
Claim 8
Dependent Claim
29 words
A circuit according to claim 4, characterized in that each of said I/O cells (13, 13a - 13i) includes an input protective resistor (32) in addition to said buffer.
References Cited (Backward Citations)
No citation records indexed.
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