Junction switch for packet switching

Claim 2

A switching module comprising at least one junction switch for connecting a first bus to a second bus for transmitting digital information by way of packets having an address field and a data field, characterized in that the junction switch comprises: - a translation memory * having a data input for receiving information words from an external central control unit, * having an address input to which the address field of the packets is applied, * and having a data output; - a comparator * having an input which is connected to the data output of the translation memory, for comparing the information-word originating from this data output to a predetermined information-word, * and having an output; - a queue memory in the form of an elastic buffer * having a first data input to which the data field of the packets is applied, * having a second data input which is connected to the data output of the translation memory, * and having a write-enable input which is connected to the comparator output for bringing the queue memory into the write position; - an insertion circuit inserted into the second bus and comprising: * a detection circuit for detecting available packet space on the second bus, * and a write circuit controlled by the detection circuit for writing in the available packet space a packet originating from the data output of the queue memory.

Claim 3

A switching module as claimed in Claim 1, characterized in that the insertion circuit comprises: - a serial/parallel register for packet information which is connected in a series arrangement with the second bus * having a serial data input which is connected to the load side of the second bus, * having a serial data output which is connected to the unload side of the second bus, * having a parallel data input, * and having a parallel data output; - an address length counter * having an input which is connected to the second bus for receiving clock pulses from that bus, * having a reset input which is also connected to the second bus for receiving packet synchronization pulses from that bus, * and having an output; - a buffer * having a write-enable input which is connected to the output of the address length counter, * having a data input which is connected to the parallel data output of the serial/parallel register, * and having a data output; - a second comparator * having an input which is connected to the buffer data output for comparing the information word originating from this data output to a predetermined information word, * and having an output; - gate means for supplying the parallel data input of the serial/parallel register the packet occurring at the output of the queue memory in dependence on the signal at the output of the second comparator.

Claim 4

A switching module as claimed in Claim 1 or 2, characterized in that the junction switch comprises a second and a third buffer which are serially connected to the first and the second bus, respectively, the second and the third buffer comprising a clock input connected to the respective clock channels of the first and the second bus, and a reset input connected to the clock input through a delay element.

Claim 5

A switching module as claimed in Claim 1, 2 or 3, characterized in that the junction switch comprises a multiplexer which includes: - a first data input which is linked to the first bus, - a second data input which is connected to the central control unit, - a data output which is connected to the address input of the translation memory, - and a selection input which is connected to the external central control unit for optionally connecting the first data input to the address input of the translation memory or the second data input to the address input of the translation memory.