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EP0206403A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

High speed packet switching arrangement

Assignee: Racal Data Communications Inc
•
Filing: 1986-06-12
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Granted: —
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Expires: 2006-06-12
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Abstract

Abstract A circuit arrangement is provided for switching serial data packets through a network destined for one of a plurality of possible outgoing lines (104, 106, 108). Minimal delay is achieved by shifting the data through a shift register (120) having length equivalent to the destination address of the incoming serial data packet. The shift register addresses a memory (126) which in turn controls a switch network (138) so that the incoming packet is switched with minimal delay to an appropriate outbound line. By utilizing random access memory to translate from destination address to switch position, the system may be altered to correct for changes in the overall network caused by network failures or expansion network or to allow dynamic load balancing by directing data through the switch to a control computer (134) which in turn rewrites the memory.

Inventors

  • 👤 William Joseph Miller

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 20:13
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/20; H04L49/205; H04L49/206; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L2012/5638; H04L2012/5646; H04L2012/5649; H04L49/30; H04L49/55; H04L49/557

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 123 words
A circuit arrangement for routing incoming serial data to one of a plurality of outgoing ports, wherein said incoming serial data includes a header containing an N bit address indicative of which one of said plurality of M outgoing ports said data should be routed to, said circuit arrangement characterized by: a shift register (120) having N stages and an input (102) for receiving said serial data and an output for providing shifted data; memory means (126) having a parallel address word input coupled to each of said N stages and a memory output; and switching means (130) receiving said shifted output and responsive to said parallel memory output for selecting one of said M outgoing ports for transmission of said shifted data.
Claim 2
Dependent Claim 123 words
A circuit arrangement for routing incoming serial data to one of a plurality of outgoing ports, wherein said incoming serial data includes a header containing an N bit address indicative of which one of said plurality of M outgoing ports said data should be routed to, said circuit arrangement characterized by: a shift register (120) having N stages and an input (102) for receiving said serial data and an output for providing shifted data; memory means (126) having a parallel address word input coupled to each of said N stages and a memory output; and switching means (130) receiving said shifted output and responsive to said parallel memory output for selecting one of said M outgoing ports for transmission of said shifted data.
Claim 3
Dependent Claim 54 words
The circuit arrangement of claim 1, further characterized by delay means (132) coupled between said shift register and said switching means for delaying said shifted data by a predetermined amount of time in order to synchronize receipt of said shifted data by said switching means with said selection of one of said outgoing ports.
Claim 4
Dependent Claim 29 words
The circuit arrangement of claim 1 or 2, further characterized by decoding means (128) for translating the output of said memory means to a one of M decoded signal.
Claim 5
Dependent Claim 31 words
The circuit arrangement of claim 1 or 2, further characterized by latching means (124) for latching the parallel output of said shift register when said shift register contains said destination address.
Claim 6
Dependent Claim 26 words
The circuit arrangement of claim 4, further characterized by a computer (134) coupled to said memory means for changing the information stored in said memory means.
Claim 7
Dependent Claim 40 words
The circuit arrangement of claim 5, wherein said switching means is further characterized by a local output (138) coupled to said computer so that when said destination address includes a local address, said shifted data is transferred to said computer.
Claim 8
Dependent Claim 33 words
The circuit arrangement of claim 6, wherein said computer is operatively coupled to said memory means so that said computer may change the contents of said memory means responsive to said shifted data.

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