Patent FR1237697A successfully refreshed from Google Patents.
Patent EP0339727A2 successfully refreshed from Google Patents.
EP0339727A2
Expired / Lapsed
EP
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Circuit arrangement for producing a binary signal
Assignee: Philips Electronics UK Ltd
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Filing: 1989-04-21
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Granted: —
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Expires: 2009-04-21
Abstract
Abstract A precoded duobinary signal is applied to first inputs of two voltage comparators (CP1, CP2) whose second inputs receive reference voltages appropriate to required slicing levels. The output of each comparator (CP1, CP2) is applied to respective inputs of an exclusive NOR gate (G) the output of which provides a binary signal dependent on the duobinary signal input. This duobinary input is also applied to peak rectifier circuits (D1, C1; D2, C2) whose outputs are connected to respective ends of a voltage divider (R1, R2, R3) from which the reference voltages for the comparators (CP1, CP2) are derived.
Inventors
- 👤 Bruce Murray
- 👤 Philip Harvey Bird
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 21:15
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K5/082; H04; H04N; H04N7/00; H04N7/025; H04N7/035; H04N7/0355; H04N7/08; H04N7/083
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
163 words
A circuit arrangement for producing a binary signal output from a precoded duobinary signal input, characterised in that said arrangement comprises first and second voltage comparators each having a signal input to which said duobinary signal is applied and a reference voltage input, the reference voltage input of said first comparator determining a first slicing level in said applied signal whilst the corresponding input of said second comparator determines a second slicing level in said applied signal, the outputs of said comparators being applied to respective inputs of a gate circuit having a logic function such that the said binary signal can be derived from the gate circuit output, said duobinary signal being additionally applied to first and second peak rectifier circuits for respectively producing voltages determined by the upper and the lower peaks in said duobinary signal which voltages are applied to respective ends of a voltage divider, and means for deriving said first and second reference voltages from said voltage divider.
Claim 2
Dependent Claim
163 words
A circuit arrangement for producing a binary signal output from a precoded duobinary signal input, characterised in that said arrangement comprises first and second voltage comparators each having a signal input to which said duobinary signal is applied and a reference voltage input, the reference voltage input of said first comparator determining a first slicing level in said applied signal whilst the corresponding input of said second comparator determines a second slicing level in said applied signal, the outputs of said comparators being applied to respective inputs of a gate circuit having a logic function such that the said binary signal can be derived from the gate circuit output, said duobinary signal being additionally applied to first and second peak rectifier circuits for respectively producing voltages determined by the upper and the lower peaks in said duobinary signal which voltages are applied to respective ends of a voltage divider, and means for deriving said first and second reference voltages from said voltage divider.
Claim 3
Dependent Claim
50 words
A circuit arrangement as claimed in Claim 1, characterised in that each of said comparators comprises a differential amplifier where the non-inverting input forms the signal input whilst the inverting input forms the reference voltage input whilst said gate circuit is an exclusive OR gate or an exclusive NOR gate.
Claim 4
Dependent Claim
71 words
A circuit arrangement as claimed in Claim 1, characterised in that said first and second comparators comprise respective first and second differential amplifiers, the inverting and the non-inverting inputs of said first differential amplifier respectively receiving its reference voltage and the duobinary signal whilst the inverting and the non-inverting inputs of the second differential amplifier respectively receive the duobinary signal and its reference voltage, the gate circuit being an OR gate.
Claim 5
Dependent Claim
70 words
A circuit arrangement as claimed in Claim 1, characterised in that said first and second comparators comprise respective first and second differential amplifiers, the inverting and non-inverting inputs of said first differential amplifier respectively receiving the duobinary signal and its reference voltage whilst the inverting and the non-inverting inputs of the second differential amplifier respectively receive its reference voltage and the duobinary signal, the gate circuit being a NAND gate.
Claim 6
Dependent Claim
109 words
A circuit arrangement as claimed in Claim 1, characterised in that said first and second comparators each comprise first and second transistors having their emitters commoned, the collector of the first transistor of both comparators being directly connected to a supply voltage while the collectors of the second transistor of both comparators are connected through a common load to said supply voltage, said duobinary signal being applied to the base of the first transistor in the first comprator and to the base of the second transistor in the second comparator while the bases of the remaining transistor in each comparator receive either the first or the second reference voltage.
Claim 7
Dependent Claim
90 words
A circuit arrangement as claimed in Claim 1, 2, 3, 4 or 5, characterised in that said arrangement additionally comprising a third voltage comparator having a signal input for receiving a binary input signal and a reference voltage input determining a slicing level in said binary signal which reference voltage input is connected to said voltage divider, means for connecting the output of said gate circuit and that of said third comparator to a selector circuit for selecting the appropriate binary output dependent on the nature of the input signal.
Claim 8
Dependent Claim
26 words
A precoded duobinary to binary sigal converter comprising first and second differential amplifiers and a gate circuit as claimed in Claim 2, 3, 4 or 5.
References Cited (Backward Citations)
No citation records indexed.
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