Patent EP0339637A2 successfully refreshed from Google Patents.
EP0339637A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
LSI semiconductor device
Assignee: Toshiba Corp
•
Filing: 1989-04-27
•
Granted: —
•
Expires: 2009-04-27
Abstract
Abstract A semiconductor device having CMOS transistors and bipolar transistors is disclosed. A P-type high concentration buried region (16a) is formed in the surface region of the semiconductor substrate (10). An N-type epitaxial layer is formed on the buried region (16a). The semiconductor device includes a second well region (15) of a PMOS transistor that is formed by introducing an N-type impurity into a part of the epitaxial layer, and a first well region (14) of a bipolar transistor that is formed without introducing the N-impurity, after the formation of the epitaxial layer.
Inventors
- 👤 Takeo Intellectual Property Division Maeda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 12:53
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10W; H10W15/00; H10W15/01; H10B; H10B69/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
221 words
A semiconductor device having a bipolar transistor and a CMOS transistor comprising: a semiconductor substrate (10) of a first conductivity type; a first high concentration buried region (16a) of the first conductivity type for preventing punch-through and soft error, said buried region (16a) being formed on said semiconductor substrate (10); second and third high concentration buried regions (13a, 13) of a second conductivity formed on said semiconductor substrate (10) and located on both sides of said first high concentration buried region (16a); a first well region (14) of the second conductivity type formed on said third high concentration buried region (13) of the second conductivity, a bipolar transistor being formed in the surface region of said first well region (14); a second well region (15) of the second conductivity type formed on said second high concentration buried region (13a) of the second conductivity, a first channel MOS transistor being formed in the surface region of said second well region (15), and an impurity concentration of said second well region (15) being higher than that of said first well region (14); and a third well region (16) of the first conductivity type formed on said high concentration buried region (16a) of the first conductivity type, a second channel MOS transistor being formed in the surface region of said third well region (16).
Claim 2
Dependent Claim
221 words
A semiconductor device having a bipolar transistor and a CMOS transistor comprising: a semiconductor substrate (10) of a first conductivity type; a first high concentration buried region (16a) of the first conductivity type for preventing punch-through and soft error, said buried region (16a) being formed on said semiconductor substrate (10); second and third high concentration buried regions (13a, 13) of a second conductivity formed on said semiconductor substrate (10) and located on both sides of said first high concentration buried region (16a); a first well region (14) of the second conductivity type formed on said third high concentration buried region (13) of the second conductivity, a bipolar transistor being formed in the surface region of said first well region (14); a second well region (15) of the second conductivity type formed on said second high concentration buried region (13a) of the second conductivity, a first channel MOS transistor being formed in the surface region of said second well region (15), and an impurity concentration of said second well region (15) being higher than that of said first well region (14); and a third well region (16) of the first conductivity type formed on said high concentration buried region (16a) of the first conductivity type, a second channel MOS transistor being formed in the surface region of said third well region (16).
Claim 3
Dependent Claim
44 words
A semiconductor device according to claim 1, characterized in that said first well region (14) is used while being doped with no impurity after formation of an epitaxial layer that is formed on said first, second and third high concentration regions (16a, 13a, 13).
Claim 4
Dependent Claim
33 words
A semiconductor device according to claim 2, characterized in that said epitaxial layer contains N-type impurity at an impurity concentration in the range of 5 × 10¹⁵ cm⁻³ to 2 × 10¹⁶ cm⁻³.
Claim 5
Dependent Claim
15 words
A semiconductor device according to claim 3, characterized in that said N-type impurity is phosphorus.
Claim 6
Dependent Claim
26 words
A semiconductor device according to claim 1, characterized in that said CMOS transistor includes a PMOS transistor having a gate length of shorter than 0.8 µm.
Claim 7
Dependent Claim
280 words
A semiconductor device having a bipolar transistor and a CMOS transistor comprising: a semiconductor substrate (10) of a first conductivity type; a high concentration buried region (9a) of the first conductivity type for preventing punch-through, said buried region (9a) being formed on a portion to be used for a peripheral circuit of said semiconductor substrate (10); a second high concentration buried region (8) of the first conductivity type for preventing soft error formed in a portion to be used as a memory cell portion of said substrate (10), an impurity concentration of said buried region (8) being higher than that of said first buried region (9a); third and fourth high concentration buried regions (13a, 13) of a second conductivity type formed on said semiconductor substrate (10) and located on both sides of said first high concentration buried region (9a); a first well region (14) of the second conductivity type formed on said fourth third high concentration buried region (13b) of the second conductivity type, a bipolar transistor being formed in the surface region of said first well region (14); a second well region (15) of the second conductivity type formed on said second high concentration buried region (13a), a first channel MOS transistor being formed in the surface region of said second well region (15), and an impurity concentration of said second well region (15) being higher than that of said first well region (14); and third and fourth well regions (16a, 16b) of the first conductivity type formed on said first and second high concentration buried regions (9a, 8), a second channel MOS transistor being formed in the surface region of said third and fourth well regions (16a, 16b).
Claim 8
Dependent Claim
280 words
A semiconductor device having a bipolar transistor and a CMOS transistor comprising: a semiconductor substrate (10) of a first conductivity type; a high concentration buried region (9a) of the first conductivity type for preventing punch-through, said buried region (9a) being formed on a portion to be used for a peripheral circuit of said semiconductor substrate (10); a second high concentration buried region (8) of the first conductivity type for preventing soft error formed in a portion to be used as a memory cell portion of said substrate (10), an impurity concentration of said buried region (8) being higher than that of said first buried region (9a); third and fourth high concentration buried regions (13a, 13) of a second conductivity type formed on said semiconductor substrate (10) and located on both sides of said first high concentration buried region (9a); a first well region (14) of the second conductivity type formed on said fourth third high concentration buried region (13b) of the second conductivity type, a bipolar transistor being formed in the surface region of said first well region (14); a second well region (15) of the second conductivity type formed on said second high concentration buried region (13a), a first channel MOS transistor being formed in the surface region of said second well region (15), and an impurity concentration of said second well region (15) being higher than that of said first well region (14); and third and fourth well regions (16a, 16b) of the first conductivity type formed on said first and second high concentration buried regions (9a, 8), a second channel MOS transistor being formed in the surface region of said third and fourth well regions (16a, 16b).
Claim 9
Dependent Claim
46 words
A semiconductor device according to claim 6, characterized in that said first well region (14) is used while being doped with no impurity after formation of an epitaxial layer that is formed on said first, second, third and fourth high concentration regions (9a, 8, 13a, 13b).
Claim 10
Dependent Claim
33 words
A semiconductor device according to claim 7, characterized in that said epitaxial layer contains N-type impurity at an impurity concentration in the range of 5 × 10¹⁵ cm⁻³ to 2 × 10¹⁶ cm⁻³.
Claim 11
Dependent Claim
15 words
A semiconductor device according to claim 8, characterized in that said N-type impurity is phosphorus.
Claim 12
Dependent Claim
42 words
A semiconductor device according to claim 6, characterized in that said second high concentration buried region (8) is isolated from said high concentration buried region of the first conductivity type located adjacent to said buried region (8) by at least 2 µm.
Claim 13
Dependent Claim
26 words
A semiconductor device according to claim 6, characterized in that said CMOS transistor includes a PMOS transistor having a gate length of shorter than 0.8 µm.
Claim 14
Independent Claim
250 words
A method of manufacturing a semiconductor device having a bipolar transistor and a CMOS transistor comprising the steps of: preparing a semiconductor substrate (10) of a first conductivity type; forming a first high concentration buried region (16a) of the first conductivity type formed on said semiconductor substrate (10), and second and third high concentration buried regions (13a, 13) of a second conductivity formed on both sides of said first high concentration buried region (16a); forming an epitaxial layer of the second conductivity type on said first, second and third high concentration buried regions (16a, 13a, 13); introducing an impurity of the second conductivity type into a portion above said second high concentration buried region (13a) in said epitaxial layer, and introducing an impurity of the first conductivity type into a portion above said first high concentration buried region (16a) in said epitaxial layer, a portion of said epitaxial layer on said third region (13) serving as a first well region (14), a portion of said epitaxial layer on said first region (13a) serving as a second well region (15) whose impurity concentration is higher than that of said first well region (14), and a portion of said epitaxial layer on said second region (16a) serving as a third well region (16); and forming a bipolar transistor in said said first well region (14), and CMOS transistors in said second and third well regions (15, 16), the anneal for forming said transistors being performed within 10 minutes at 1050°C or more.
Claim 15
Independent Claim
250 words
A method of manufacturing a semiconductor device having a bipolar transistor and a CMOS transistor comprising the steps of: preparing a semiconductor substrate (10) of a first conductivity type; forming a first high concentration buried region (16a) of the first conductivity type formed on said semiconductor substrate (10), and second and third high concentration buried regions (13a, 13) of a second conductivity formed on both sides of said first high concentration buried region (16a); forming an epitaxial layer of the second conductivity type on said first, second and third high concentration buried regions (16a, 13a, 13); introducing an impurity of the second conductivity type into a portion above said second high concentration buried region (13a) in said epitaxial layer, and introducing an impurity of the first conductivity type into a portion above said first high concentration buried region (16a) in said epitaxial layer, a portion of said epitaxial layer on said third region (13) serving as a first well region (14), a portion of said epitaxial layer on said first region (13a) serving as a second well region (15) whose impurity concentration is higher than that of said first well region (14), and a portion of said epitaxial layer on said second region (16a) serving as a third well region (16); and forming a bipolar transistor in said said first well region (14), and CMOS transistors in said second and third well regions (15, 16), the anneal for forming said transistors being performed within 10 minutes at 1050°C or more.
Claim 16
Dependent Claim
22 words
The method according to claim 12, characterized in that the impurity contained in said first high concentration buried region (16a) is boron.
Claim 17
Dependent Claim
25 words
The method according to claim 12, characterized in that said CMOS transistor includes a PMOS transistor having a gate length of shorter than 0.8 µm.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.