Patent EP0338558A2 successfully refreshed from Google Patents.
EP0338558A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Packet switch suitable for integrated circuit implementation
Assignee: NEC Corp
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Filing: 1989-04-20
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Granted: —
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Expires: 2009-04-20
Abstract
Abstract The invention relates to a packet switch for exchanging packets received over a plurality of input lines (200) and outputting exchanged packets, to a plurality of output lines (213), comprising: multiplexing means (202) for time-division multiplexing the packets received over said plurality of input lines to multiplexed packets; address detecting means (204) for detecting an address of each packet in the multiplexed packets to produce a destination address; write address generating means (104) responsive to the destination address for generating write address; read address generating means (105) for sequentially generating read addresses; memory means (103) constituted by a plurality of memory areas individually associated with said plurality of output lines, said memory means responsive to said write address for storing each packet of the multiplexed packets in any of said memory areas, and responsive to said read addresses for producing exchanged multiplexed packets by reading the stored packets; and demultiplexing means (212) for demultiplexing said exchanged multiplexed packets into said exchanged packets and delivering them to said plurality of output lines.
Inventors
- 👤 Takao C/O Nec Corporation Takeuchi
- 👤 Hiroshi C/O Nec Corporation Suzuki
- 👤 Susumu C/O Nec Corporation Iwasaki
- 👤 Hiroshi C/O Nec Corporation Nagano
- 👤 Toshio C/O Nec Corporation Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 17:47
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/10; H04L49/103; H04L49/15; H04L49/1515; H04L49/1523; H04L49/30; H04L49/3018
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
159 words
A packet switch for exchanging packets received over a plurality of input lines and outputting exchanged packets, to a plurality of output lines, comprising: multiplexing means for time-division multiplexing the packets received over said plurality of input lines to multiplexed packets; address detecting means for detecting an address of each packet in the multiplexed packets to produce a destination address; write address generating means responsive to the destination address for generating write address; read address generating means for sequentially generating read addresses; memory means constituted by a plurality of memory areas individually associated with said plurality of output lines, said memory means responsive to said write address for storing each packet of the multiplexed packets in any of said memory areas, and responsive to said read addresses for producing exchanged multiplexed packets by reading the stored packets; and demultiplexing means for demultiplexing said exchanged multiplexed packets into said exchanged packets and delivering them to said plurality of output lines.
Claim 2
Dependent Claim
159 words
A packet switch for exchanging packets received over a plurality of input lines and outputting exchanged packets, to a plurality of output lines, comprising: multiplexing means for time-division multiplexing the packets received over said plurality of input lines to multiplexed packets; address detecting means for detecting an address of each packet in the multiplexed packets to produce a destination address; write address generating means responsive to the destination address for generating write address; read address generating means for sequentially generating read addresses; memory means constituted by a plurality of memory areas individually associated with said plurality of output lines, said memory means responsive to said write address for storing each packet of the multiplexed packets in any of said memory areas, and responsive to said read addresses for producing exchanged multiplexed packets by reading the stored packets; and demultiplexing means for demultiplexing said exchanged multiplexed packets into said exchanged packets and delivering them to said plurality of output lines.
Claim 3
Dependent Claim
114 words
A packet switch having a plurality of input lines and a plurality of output lines and exchanging packets received over said input lines and delivering exchanged packets to said output lines, comprising: packet generating means for generating multiplexed packets based on packets received over said plurality of input lines; a plurality of control means each being associated with respective one of said plurality of output lines for temporarily storing only necessary one of the multiplexed packets and then delivering said necessary packet as said exchanged packet to associated one of said output lines, and distributing means for distributing the multiplexed packets from said packet generating means to all of said plurality of control means.
Claim 4
Dependent Claim
114 words
A packet switch having a plurality of input lines and a plurality of output lines and exchanging packets received over said input lines and delivering exchanged packets to said output lines, comprising: packet generating means for generating multiplexed packets based on packets received over said plurality of input lines; a plurality of control means each being associated with respective one of said plurality of output lines for temporarily storing only necessary one of the multiplexed packets and then delivering said necessary packet as said exchanged packet to associated one of said output lines, and distributing means for distributing the multiplexed packets from said packet generating means to all of said plurality of control means.
Claim 5
Dependent Claim
94 words
A packet switch as claimed in claim 2, wherein each of said plurality of control means comprises: address detecting means for detecting a destination address for its own control means to produce a detected signal; write address generator means responsive to said detected signal for generating a write address; read address generator means for generating a read address; memory means responsive to the detected signal and the write address for storing said necessary one of the multiplexed packets and delivering the stored packet to the associated output line in response to the read address.
Claim 6
Dependent Claim
70 words
A packet switch as claimed in claim 2 or 3, wherein said packet generating means and said distributing means comprises: a plurality of memory means each associated with said input lines for temporarily storing the packet from said input lines and sequentially producing the stored packets in response to a read clock pulse supplied from outside, and bus means responsive to said stored packets for providing said multiplexed packets thereon.
Claim 7
Dependent Claim
200 words
A packet switch having a plurality of input lines and a plurality of output lines, exchanging packets received over said input lines and delivering exchanged packets to said output lines, comprising: a plurality of first serial-to-parallel converting means each being associated with respective one of said input lines for converting the packet coming in over associated one of said input lines to first parallel data having a predetermined number of bits, while latching address information contained in said packet; packet exchange means having memory means each being associated with respective one of said output lines for receiving the first parallel data and the associated address information outputted by said plurality of first serial-to-parallel converting means and, by referencing each of said plurality of address information, for writing said associated parallel data in associated ones of said memory means; and a plurality of first parallel-to-serial converts each being associated with respective one of said plurality of output lines for reading the first parallel data out of associated one of said memory means of said control means, converting said first parallel data to first serial data, and delivering said first serial data as exchanged packet to associated one of said output lines.
Claim 8
Dependent Claim
200 words
A packet switch having a plurality of input lines and a plurality of output lines, exchanging packets received over said input lines and delivering exchanged packets to said output lines, comprising: a plurality of first serial-to-parallel converting means each being associated with respective one of said input lines for converting the packet coming in over associated one of said input lines to first parallel data having a predetermined number of bits, while latching address information contained in said packet; packet exchange means having memory means each being associated with respective one of said output lines for receiving the first parallel data and the associated address information outputted by said plurality of first serial-to-parallel converting means and, by referencing each of said plurality of address information, for writing said associated parallel data in associated ones of said memory means; and a plurality of first parallel-to-serial converts each being associated with respective one of said plurality of output lines for reading the first parallel data out of associated one of said memory means of said control means, converting said first parallel data to first serial data, and delivering said first serial data as exchanged packet to associated one of said output lines.
Claim 9
Dependent Claim
276 words
A packet switch as claimed in claim 5, wherein said packet exchange means comprises a plurality of unit packet exchange means each being associated with respective one of bits of the first parallel data, said unit packet exchange means each comprising: a plurality of second serial-to-parallel converting means each being associated with said plurality of first serial-to-parallel converting means for receiving the associated bits of the first parallel data as input serial data, converting said input serial data into second parallel data having a second predetermined number of bits, combining the address information being latched by said associated serial-to-parallel converting means with said second parallel data to produce third parallel data; a plurality of address filter means each being associated with said plurality of output lines for determining whether or not the third parallel data is meant for said associated output line by referencing the address information of the third parallel data and, if a result of decision is positive, outputting the second parallel data by removing said address information from said third parallel data; a bus means for distributing the third parallel data from one of the second serial-to-parallel converting means to all of the address filter means; memory means each being associated with said address filter means for holding as write data the second parallel data which is outputted by associated one of said address filter means and outputting said held second parallel data at a predetermined period; and second parallel-to-serial converting means each being associated with said memory means for converting the second parallel data outputted by associated one of said memory means to second serial data and outputting said second serial data.
References Cited (Backward Citations)
No citation records indexed.
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