CMOS to GPI general purpose interface interface circuit

Abstract

Abstract A high speed, high performance CMOS to GPI interface circuit is disclosed. The interface circuit contains an input stage (21), clamping circuitry (22), an output stage (23) and feed­back circuitry (26). The clamping circuitry (22) clamps the voltage level presented to the output stage (23) at a level below the power supply voltage when the input from the CMOS circuit is at a high logic level. As the voltage level of the signal presented to the GPI circuitry rises, feedback circuitry (26) feeds this signal back to the clamping circuit­ry, which in turn decreases the voltage level presented to the output stage. This assures the signal presented to the GPI circuit falls within the speci-fied voltage level from 1.51 and 2.2 volts. The feedback circuitry (26) contains a single pole filter that filters out high frequency reflections presented to the feedback circuitry (26), and a slew rate limiter that slows the rise and fall of the voltage level presented to the output stage (23) thereby reducing noise on the power supply and ground lines. The feedback circuitry (26) uses bilateral (push-pull) gain tech­niques to control the voltage level presented to the output stage (23) as the input signal from the CMOS circuit swings from low to high logic levels. The interface circuit is made up exclusively from standard threshold FETs. The interface circuit also contains discharge circuitry (24) that discharges the voltage level of the feed­back circuitry (26) when the input from the CMOS circuit chang­es from a high level to a low level, thereby preventing a latch-up condition.

Inventors

• 👤 Delbert Raymond Cecchi
• 👤 Hyung Sun Kim
• 👤 John Steven Mitby
• 👤 David Peter Swart
• 👤 Balsha Robert Stanisic
• 👤 Philip Tung Wu

Bibliographic Details