Patent EP0335741A2 successfully refreshed from Google Patents.
EP0335741A2
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Dielectrically isolated semiconductor substrate
Assignee: Toshiba Corp
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Filing: 1989-03-31
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Granted: —
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Expires: 2009-03-31
Abstract
Abstract A dielectrically isolated semiconductor wafer substrate includes first and second semiconductive layers bonded to each other by a direct bonding technique in such a manner that an insulative layer is sandwiched therebetween. The first semiconductive layer is a first silicon layer having a (100) or (110) crystal surface orientation, while the second semiconductive layer is a second silicon layer having a (111) crystal surface orientation. Thereafter, a peripheral portion of the resultant substrate is removed, and a substrate of a slightly smaller size is obtained which is provided with an additionally formed new orientation flat.
Inventors
- 👤 Yoshihiro C/O Patent Division Yamaguchi
- 👤 Kiminori C/O Patent Division Watanabe
- 👤 Akio C/O Patent Division Nakagawa
- 👤 Kazuyoshi C/O Patent Division Furukawa
- 👤 Kiyoshi C/O Patent Division Fukuda
- 👤 Katsujiro C/O Patent Division Tanzawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 16:57
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10P10/00; H10P10/12; H10W; H10W10/00; H10W10/10; H10W10/181; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/159
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
74 words
A semiconductor substrate comprising a first semiconductive layer (10), a second semiconductive layer (12) to be bonded to said first semiconductive layer, and an insulative layer (14b) sandwiched between said first and second semiconductive layers (10, 12), characterized in that said first semiconductive layer is a first silicon layer having a (100) or (110) crystal surface orientation, and that said second semiconductive layer is a second silicon layer having a (111) crystal surface orientation.
Claim 2
Dependent Claim
74 words
A semiconductor substrate comprising a first semiconductive layer (10), a second semiconductive layer (12) to be bonded to said first semiconductive layer, and an insulative layer (14b) sandwiched between said first and second semiconductive layers (10, 12), characterized in that said first semiconductive layer is a first silicon layer having a (100) or (110) crystal surface orientation, and that said second semiconductive layer is a second silicon layer having a (111) crystal surface orientation.
Claim 3
Dependent Claim
41 words
The substrate according to claim 1, characterized in that said first silicon layer (10) serves as an active layer on which integrated circuit elements are formed, while said second silicon layer serves as a base layer for supporting said active layer.
Claim 4
Dependent Claim
19 words
The substrate according to claim 2, characterized in that said insulative layer includes a silicon oxide thin film (14b).
Claim 5
Dependent Claim
39 words
The substrate according to claim 3, characterized in that said first and second silicon layers (10, 12) bonded to each other are provided with a peripheral portion which is removed after said first and second silicon layers are bonded.
Claim 6
Dependent Claim
26 words
The substrate according to claim 4, characterized in that said first and second silicon layers (10, 12) are provided with an additionally formed orientation flat (24).
Claim 7
Independent Claim
104 words
A method of manufacturing a dielectrically isolated semiconductor substrate, characterized by comprising the steps of forming an insulative layer (14b) on a first semiconductive layer (10), said first semiconductive layer being a first silicon layer (10) having a (100) or (110) crystal surface orientation, bonding a second semiconductive layer (12) to said first semiconductive layer (10) in such a manner that said insulative layer (14b) is sandwiched therebetween to provide a bonded substrate, said second semiconductive layer being a second silicon layer (12) having a (111) crystal surface orientation, and removing a peripheral portion of said bonded substrate to provide a processed substrate (16′).
Claim 8
Independent Claim
104 words
A method of manufacturing a dielectrically isolated semiconductor substrate, characterized by comprising the steps of forming an insulative layer (14b) on a first semiconductive layer (10), said first semiconductive layer being a first silicon layer (10) having a (100) or (110) crystal surface orientation, bonding a second semiconductive layer (12) to said first semiconductive layer (10) in such a manner that said insulative layer (14b) is sandwiched therebetween to provide a bonded substrate, said second semiconductive layer being a second silicon layer (12) having a (111) crystal surface orientation, and removing a peripheral portion of said bonded substrate to provide a processed substrate (16′).
Claim 9
Dependent Claim
26 words
The method according to claim 6, characterized in that each of said first and second silicon layers (10, 12) has an initially formed orientation flat (18).
Claim 10
Dependent Claim
28 words
The method according to claim 7, characterized in that said initially formed orientation flat (18) is removed when the peripheral portion of said bonded substrate (16) is removed.
Claim 11
Dependent Claim
24 words
The method according to claim 8, characterized by further comprising the step of additionally forming an orientation flat (24) on said processed substrate (16′).
Claim 12
Dependent Claim
26 words
The method according to claim 9, characterized in that said first silicon layer (10) is polished on an exposed surface thereof to have a decreased thickness.
Claim 13
Dependent Claim
29 words
The method according to claim 10, characterized in that said first silicon layer (10) serves as an active layer by forming integrated circuit elements on a polished surface thereof.
Claim 14
Dependent Claim
35 words
The method according to claim 11, characterized in that insulating layers (40, 42) serving as insulating isolation layers of said integrated circuit elements are buried in said polished surface of said first silicon layer (10′).
References Cited (Backward Citations)
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