Microcontroller and associated method

Claim 2

A VLSI microcontroller comprising: first means for processing digital information; second internal means for storing digital information, said second means including a plurality of memory locations; an internal bus for conducting digital information to and from said first means and said second means; a plurality of first external terminals; third means for transferring digital information between said internal bus and said plurality of first external terminals, said third means being operable in either a port mode or a bus mode; wherein said third means in the bus mode transfers digital information only upon a provision of first digital information on said internal bus; and wherein said third means in the port mode transfers digital information only upon a provision of second digital information on said internal bus.

Claim 3

The VLSI microcontroller of Claim 1 wherein: said first digital information includes at least one first prescribed address byte which corresponds to none of said plurality of memory locations.

Claim 4

The microcontroller of Claim 2 wherein: said third means in the bus mode selectively transfers digital information from said first external terminals to said internal bus only upon the provision of the at least one first prescribed address byte.

Claim 5

The VLSI microcontroller of Claim 3 wherein: said first means provides at least one IREAD control signal and at least one IWRITE control signal; said third means, in the bus mode, transfers digital information from said internal bus to said first external terminals in response to the at least one IWRITE control signal; and said third means, in the bus mode, transfers digital information from said first external terminals to said internal bus in response to the at least one IREAD control signal in combination with the at least one first prescribed address byte.

Claim 6

The VLSI microcontroller of Claim 4 and further comprising: fourth means for controlling said third means such that in the bus mode said third means can transfer digital information from said first external terminals to said internal bus only when said first means provides the at least one IREAD control signal in the course of a provision of the at least one first prescribed address byte on said internal bus.

Claim 7

The VLSI microcontroller of Claim 5 wherein said fourth means further comprises: first decoding means for decoding the at least one prescribed first address byte.

Claim 8

The VLSI microcontroller of Claim 1 wherein: said second digital information includes at least one second prescribed address byte; and said third means, in the port mode, selectively transfers digital information between said first external terminals and said internal bus only upon the provision of the at least one second prescribed address byte.

Claim 9

The microcontroller of Claim 7 wherein: said third means, in the port mode, can transfer digital information between said internal bus and said first external terminals only upon the provision of at least one second prescribed address byte.

Claim 10

The VLSI microcontroller of Claim 8 wherein said third means includes: second decoding means for decoding the at least one second prescribed address byte provided on said internal bus.

Claim 11

The VLSI microcontroller of Claim 9 wherein: said first means provides at least one IREAD control signal and at least one IWRITE control signal; said third means, in the port mode, transfers digital information from said plurality of first external terminals to said internal bus in response to the at least one IREAD control signal in combination with the at least one second prescribed address byte; and said third means, in the port mode, transfers digital information from said internal bus to said plurality of first external terminals in response to the at least one IWRITE control signal in combination with the at least one second prescribed address byte.

Claim 12

The VLSI microcontroller of Claim 1 wherein: said third means includes at least one first latch means and at least one second latch means, for sequentially latching at least one respective bit of digital information in the course of transfers of digital information from said internal bus to said first external terminals; said third means, in the port mode, in the course of a transfer of digital information from said internal bus to said external terminals sequentially latches at least one respective bit in said at least one first latch means, and subsequently, latches the at least one respective bit in said at least one second latch means; and said third means, in the bus mode, in the course of a transfer of digital information from said internal bus to said external terminals latches at least one respective bit in said at least one first latch means and bypasses the at least one respective bit past said at least one second latch means.

Claim 13

The microcontroller of Claim 1 wherein said third means further comprises: respective driver circuits for driving digital information transferred from said internal bus to said first external terminals such that the digital information can be propagated externally from said first external terminals; and means for preventing said respective driver circuits from driving in the course of a transfer of digital information from said first external terminals to said internal bus.

Claim 14

A VLSI microcontroller comprising: first means for processing digital information; second internal memory means including a plurality of memory locations; an internal bus for conducting digital information to and from said first means and said second means; a plurality of first external terminals; third means for transferring digital information between said internal bus and said plurality of first external terminals, said third means being operable in either a port mode or a bus mode; first decoding means for decoding at least one first byte; second decoding means for decoding at least one second byte; wherein said third means, in the bus mode, can transfer digital information from the first external terminals to said internal bus only upon the provision of the at least one first byte; and wherein said third means, in the port mode, can transfer digital information between said internal bus and said first external terminals only upon the provision of at least one second byte.

Claim 15

A VLSI microcontroller comprising: first means for processing digital information; second internal memory means including a plurality of memory locations; an internal bus for conducting digital information to and from said first means and said second means; a plurality of first external terminals; third means for transferring digital information between said internal bus and said plurality of first external terminals, said third means being operable in either a port mode or a bus mode; first decoding means for decoding at least one first byte; second decoding means for decoding at least one second byte; wherein said third means, in the bus mode, can transfer digital information from the first external terminals to said internal bus only upon the provision of the at least one first byte; and wherein said third means, in the port mode, can transfer digital information between said internal bus and said first external terminals only upon the provision of at least one second byte.

Claim 16

The VLSI microcontroller of Claim 13 wherein: said first means provides at least one IREAD control signal and at least one IWRITE control signal; said third means, in the bus mode, transfers digital information from said internal bus to said first external terminals in response to the at least one IWRITE control signal; said third means, in the bus mode, transfers digital information from said first external terminals to said internal bus in response to the at least one IREAD control signal in combination with the at least one first byte; said third means, in the port mode, transfers digital information from said plurality of first external terminals to said internal bus in response to the at least one IREAD control signal in combination with the at least one second byte; and said third means, in the port mode, transfers digital information from said internal bus to said plurality of first external terminals in response to the at least one IWRITE control signal in combination with the at least one second byte.

Claim 17

The VLSI microcontroller of Claims 1 or 13 and further comprising: second external terminals; and timing means for providing timing signals to said second external terminals, said timing signals substantially contemporaneously indicating when respective types of digital information are required to be provided on said internal bus in the course of an execution of a respective instruction by said first means.

Claim 18

The VLSI microcontroller of Claim 15 wherein: said timing signals can indicate when each of at least three types of digital information are required to be provided on said internal bus in the course of an execution of a respective instruction by said first means.

Claim 19

The VLSI microcontroller of Claim 16 wherein: said at least three types of digital information respectively represent at least one address location, data to be provided to said first means and data provided by said first means.

Claim 20

The VLSI microcontroller of Claim 15 wherein: said first means (22) provides respective control signals; and said timing means (32, 64) is responsive to the respective control signals.

Claim 21

The VLSI microcontroller of Claim 18 wherein: said first means provides at least one IWRITE control signal, at least one IREAD control signal and at least one IADDRESS control signal; and said timing means is respectively responsive to the at least one IWRITE control signal, the at least one IREAD control signal and the at least one IADDRESS control signal.

Claim 22

The VLSI microcontroller of Claim 13 which includes no more than two second external terminals.

Claim 23

The VLSI microcontroller of Claim 13 wherein the at least one first byte is an address signal byte which corresponds to none of said plurality of memory locations.

Claim 24

The VLSI microcontroller of Claim 21 wherein said third means, in the bus mode, provides said at least one first byte to said plurality of first external terminals.

Claim 25

A VLSI microcontroller comprising: first means for processing digital information; wherein said first means provides at least one IREAD control signal and at least one IWRITE control signal; second means for storing digital information, said second means including a plurality of memory locations; an internal bus for conducting digital information to and from said first means and said second means; a plurality of first external terminals; said second means being operable in either a port mode or a bus mode; third means for transferring digital information between said internal bus and said plurality of first external terminals, said third means being operable in either a port mode or a bus mode; first decoding means for decoding at least one first address byte; second decoding means for decoding at least one second address byte; wherein said third means, in the bus mode, transfers digital information from said internal bus to said first external terminals in response to the at least one IWRITE control signal; wherein said third means, in the bus mode, transfers digital information from said first external terminals to said internal bus in response to the at least one IREAD control signal in combination with the at least one first address byte; wherein said third means, in the port mode, transfers digital information from said plurality of first external terminals to said internal bus in response to the at least one IREAD control signal in combination with the at least one second address byte; wherein said third means, in the port mode, transfers digital information from said internal bus to said plurality of first external terminals in response to the at least one IWRITE control signal in combination with the at least one second address byte; no more than two second external terminals; and timing means for providing timing signals to said second external terminals, said timing signals substantially contemporaneously indicating when respective types of digital information are required to be provided on said internal bus in the course of an execution of a respective instruction by said first means; and wherein said timing means is responsive to the at least one IREAD control signal and to the at least one IWRITE control signal.

Claim 26

A VLSI microcontroller comprising: first means for processing digital information; wherein said first means provides at least one IREAD control signal and at least one IWRITE control signal; second means for storing digital information, said second means including a plurality of memory locations; an internal bus for conducting digital information to and from said first means and said second means; a plurality of first external terminals; said second means being operable in either a port mode or a bus mode; third means for transferring digital information between said internal bus and said plurality of first external terminals, said third means being operable in either a port mode or a bus mode; first decoding means for decoding at least one first address byte; second decoding means for decoding at least one second address byte; wherein said third means, in the bus mode, transfers digital information from said internal bus to said first external terminals in response to the at least one IWRITE control signal; wherein said third means, in the bus mode, transfers digital information from said first external terminals to said internal bus in response to the at least one IREAD control signal in combination with the at least one first address byte; wherein said third means, in the port mode, transfers digital information from said plurality of first external terminals to said internal bus in response to the at least one IREAD control signal in combination with the at least one second address byte; wherein said third means, in the port mode, transfers digital information from said internal bus to said plurality of first external terminals in response to the at least one IWRITE control signal in combination with the at least one second address byte; no more than two second external terminals; and timing means for providing timing signals to said second external terminals, said timing signals substantially contemporaneously indicating when respective types of digital information are required to be provided on said internal bus in the course of an execution of a respective instruction by said first means; and wherein said timing means is responsive to the at least one IREAD control signal and to the at least one IWRITE control signal.

Claim 27

A VLSI microcontroller comprising: processor means for processing digital information; wherein said processor means is adapted to execute direct instructions only for a prescribed set of address bytes; memory means for storing digital information, said memory means including a plurality of memory locations; wherein the prescribed set of address bytes includes at least one reserved address byte which corresponds to none of said respective memory locations; internal bus means for conducting digital information between said processor means and said memory means; a plurality of first external terminals; and transfer means for transferring the at least one reserved address byte from said internal bus means to said plurality of first external terminals on a first digital signal path and for providing a second digital signal path from said plurality of first external terminals to said internal bus means.

Claim 28

A VLSI microcontroller comprising: processor means for processing digital information; wherein said processor means is adapted to execute direct instructions only for a prescribed set of address bytes; memory means for storing digital information, said memory means including a plurality of memory locations; wherein the prescribed set of address bytes includes at least one reserved address byte which corresponds to none of said respective memory locations; internal bus means for conducting digital information between said processor means and said memory means; a plurality of first external terminals; and transfer means for transferring the at least one reserved address byte from said internal bus means to said plurality of first external terminals on a first digital signal path and for providing a second digital signal path from said plurality of first external terminals to said internal bus means.

Claim 29

The VLSI microcontroller of Claim 24 wherein: said processor means selectively provides IREAD control signals and IWRITE control signals; and said transfer means transfers the at least one reserved address byte in response to at least one IWRITE control signal; and said transfer means provides said second digital signal path in response to at least one IREAD control signal.

Claim 30

The VLSI microcontroller of Claim 24 and further comprising: second external terminals; and timing means for providing timing signals to said second external terminals to indicate, in the course of the execution of a direct address instruction by said processor means, when at least one address byte is to be provided to said internal bus means, when data is to be transferred from said internal bus means to said first external terminals and when said second digital signal path from said first external terminals to said internal bus means is to be provided.

Claim 31

In a VLSI microcontroller including processor means for processing digital information, said processor means being adapted to execute direct instructions for a prescribed set of address bytes; memory means for storing digital information, said memory means including a plurality of memory locations; internal bus means for conducting digital information between said processor means and said memory means; and a plurality of external terminals, a method for executing at least one direct address instruction comprising the steps of: providing on said internal bus means at least one address byte from the prescribed set which corresponds to none of said memory locations; transferring the at least one address byte to said first external terminals; after said step of transferring, providing a first digital signal path from said first external terminals to said internal bus means.

Claim 32

In a VLSI microcontroller including processor means for processing digital information, said processor means being adapted to execute direct instructions for a prescribed set of address bytes; memory means for storing digital information, said memory means including a plurality of memory locations; internal bus means for conducting digital information between said processor means and said memory means; and a plurality of external terminals, a method for executing at least one direct address instruction comprising the steps of: providing on said internal bus means at least one address byte from the prescribed set which corresponds to none of said memory locations; transferring the at least one address byte to said first external terminals; after said step of transferring, providing a first digital signal path from said first external terminals to said internal bus means.

Claim 33

The method of Claim 27 wherein said step of transferring further comprises providing a second digital signal path from said internal bus means to said first external terminals.

Claim 34

The method of Claim 27 and further comprising the step of: Providing timing signals to second external terminals, the timing signals substantially contemporaneously indicating when respective types of digital information are required to be provided on said internal bus means in the course of the execution of the at least one direct address instruction.