Patent EP0335306B1 successfully refreshed from Google Patents.
EP0335306B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method and device for obtaining in real time the two-dimensional discrete cosine transform
Assignee: Nokia Spain SA
•
Filing: 1989-03-28
•
Granted: 1995-05-24
•
Expires: 2009-03-28
Abstract
Abstract Especially applicable to the compression of video signals. The method, which makes use of the possibility of breaking down one two-dimensional transform into two one-dimensional transforms, is characterised in that the two one-dimensional transforms are computed in time-overlapped processes, the first of these generating data for the second and the second using the data previously supplied by the first. The device consists of two multiplier sections (6, 12) separated one from the other by two FIFO memories (9, 11) which act as temporary stores, and of the selection logic (10) required to allocate at each moment the read or write function to each FIFO memory.
Inventors
- 👤 Tomas C/O Alcatel Standard Electr. Sanjuan Flores
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 19:50
CPC Classifications
G; G06; G06T; G06T9/00; G06T9/007; G06F; G06F17/00; G06F17/10; G06F17/14; G06F17/147
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
223 words
Method for obtaining in real time the two-dimensional discrete cosine transform of input signals, especially applicable to the compression of video signals, in real time with actual sequences and images, this method making use of the possibility of breaking a two-dimensional transform down into two one-dimensional transforms, the first one-dimensional discrete cosine transform matrix [P] = [C] * [X] being calculated on a row by row basis, where [ P ] is the intermediate result matrix, [C] is the coefficients matrix and [X] is the input data matrix, the method being characterised in that the second one-dimensional discrete cosine transform matrix [T] = [P] * [C t ] is calculated on a row by row basis too, from the rows of the first one-dimensional discrete cosine transform, where [T] is the final result matrix of the second one-dimensional discrete cosine transform and [C t ] is the transposed coefficients matrix, so that a row of the two-dimensional discrete cosine transform is obtained from a row of the input signals only after twice the time necessary for calculating a row of a one-dimensional discrete cosine transform, and that a full two-dimensional discrete cosine transform is obtained only after the time necessary for calculating a full one-dimensional discrete cosine transform, increased by the time necessary for calculating a row of a one-dimensional discrete cosine transform.
Claim 2
Dependent Claim
259 words
Device for applying the method of claim 1 and being formed by a first multiplier circuit (6) for calculating calculate successive rows of the first one-dimensional discrete cosine transform, that is connected to two FIFO (first in, first out) memories (9, 11), each one to store one row of the one-dimensional discrete cosine transform, which in turn are connected to a selection logic circuit (10), so that when said first multiplier circuit (6) has calculated a first row of a first one-dimensional discrete cosine transform, the result is stored into a first FIFO memory (9), and then, when said first multiplier circuit (6) has calculated a second row of said first one-dimensional discrete cosine transform, the result is stored into a the second FIFO memory (11), the device also including a second multipler circuit (12) characterized in that said second multiplier circuit (12) calculates a first row of a second one-dimensional discrete cosine transform, so that to provide one row of the final two-dimensional discrete cosine transform, as from the contents of said second FIFO memories (11), whereas said first FIFO memory (9) is storing one row of said first one-dimensional discrete cosine transform from said first multipler circuit (6), and then to calculate a second row of said second one-dimensional discrete cosine transforme, i.e. of the final two-dimensional discrete cosine transform, as from the contents of said first FIFO memories (9), whereas said second FIFO memory (11) is storing a second row of said first one-dimensional discrete cosine transform from said first multipler circuit (6), and so on.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.