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EP0335149A2
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Semiconductor memory redundancy scheme
Assignee: International Business Machines Corp
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Filing: 1989-03-09
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Granted: —
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Expires: 2009-03-09
Abstract
Abstract A semiconductor memory system in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available for each of a plurality of sub-arrays of a normal memory.
Inventors
- 👤 John Atkinson Fifield
- 👤 Howard Leo Kalter
- 👤 Christopher Paul Miller
- 👤 Steven William Tomashot
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 02:48
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/84
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
128 words
A semiconductor memory system comprising: a first array of memory cells organized as a plurality of rows and columns representing, respectively, wordlines and bit lines, said array having an associated sub-array of reference cells, at least one of which is selected whenever one of the memory cells in the first array is selected; an array of redundant memory cells; means responsive to memory address signals for indicating the selection of a redundant wordline in place of a wordline associated with the first array of memory cells; means responsive to the redundant selection means for inhibiting the generation of wordline select signals and inhibiting the selection of a reference cell; and means for the selection of at least one of the cells in said array of redundant memory cells.
Claim 2
Dependent Claim
128 words
A semiconductor memory system comprising: a first array of memory cells organized as a plurality of rows and columns representing, respectively, wordlines and bit lines, said array having an associated sub-array of reference cells, at least one of which is selected whenever one of the memory cells in the first array is selected; an array of redundant memory cells; means responsive to memory address signals for indicating the selection of a redundant wordline in place of a wordline associated with the first array of memory cells; means responsive to the redundant selection means for inhibiting the generation of wordline select signals and inhibiting the selection of a reference cell; and means for the selection of at least one of the cells in said array of redundant memory cells.
Claim 3
Dependent Claim
126 words
A semiconductor memory system, preferably of the type as recited in claim 1, comprising: a first array of memory cells organized as a plurality of rows and columns representing, respectively, wordlines and bit lines, each of the cells of the array being coupled to at least one bit line; means for coupling bit lines to respective sensing means; an array of redundant memory cells, each of the cells of which being coupled to at least one bit line; wherein the improvement comprises isolation means disposed between memory cells of the first array and redundant memory cells coupled to the same bit line such that when redundant memory cells are being sensed the memory cells of the first array are isolated from those of the redundant array.
Claim 4
Dependent Claim
27 words
The memory system as recited in one of the preceding claims wherein the redundant memory cells are of the twincell type storing signals complementary to each other.
Claim 5
Dependent Claim
53 words
The memory system as recited in one of the preceding claims wherein the redundant memory cells are placed on the sense node side of the bit or data line isolation means thus enabling the doubling of the number of redundant cells available for each of a plurality of sub-arrays of a normal memory.
Claim 6
Dependent Claim
34 words
The memory system as recited in one of the preceding claims comprising a redundant decoder circuit for the generation of a wordline drive inhibit signal which inhibits the generation of a normal wordline signal.
Claim 7
Dependent Claim
51 words
The memory system as recited in claim 5 wherein the NOR voltage nodes of the redundant decoder circuits are utilized in conjunction with an Exclusive NOR circuit to generate a wordline drive inhibit timing signal that prevents the normal wordline drive from being triggered whenever a redundant wordline decoder is selected.
Claim 8
Dependent Claim
33 words
The memory system as recited in claim 6 further comprising means for coupling the outputs of a plurality of Exclusive NOR circuits to a common node which is applied to a drive stage.
Claim 9
Dependent Claim
29 words
The memory system as recited in claim 7 comprising a filter through which the drive stage output is coupled to a wordline drive kill (VWKILL) voltage node (Fig. 7).
References Cited (Backward Citations)
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