Soft error resistant data storage cells

Abstract

Abstract A CMOS data cell having increased immunity to single event upsets is disclosed. The cell includes a first CMOS inverter (P1, N1) and a second CMOS inverter (P2, N2) which have their respective storage nodes (A, B) interconnected by cross-coupling connections. The respective storage nodes (A, B) of the cell are connected through word line or write clock transfer gates (N3, N4) to bit lines (BL, BL') or data bus lines which serve to both write in and read out the data state of the cell. The soft error resistant data cell further includes six transistors (PA, PB, PC, PD, PE, PF) which provide the hardening features to the data storage cell design. Two data state control transist­ors (PA, PB) have their drain electro­des connected to a data storage node (A, B) and their source electrodes connected to the power supply rail (+V). Each of the data state control transistors (PA, PB) is gated by the word line voltage via a transfer device or pass transistor (PC, PD). The gate electrode of each of the two data state control transistors (PA, PB) is also connected to the drain electrode of a transistor of a cross-coupled transistor pair (PE, PF).

Inventors

• 👤 Leonard R. Rockett

Bibliographic Details