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EP0334357A2
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Pulse insertion circuit
Assignee: Fujitsu Ltd
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Filing: 1989-03-23
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Granted: —
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Expires: 2009-03-23
Abstract
Abstract The pulse insertion circuit comprises a series to parallel converter (6) converting a series of input data to two parallel input data having a half clock frequency by distributing the series data alternately, a parallel type elastic memory (1) writing or reading the two parallel input data synchronously, a delay circuit (2) delaying one of the two parallel input data, a selector (3) selecting two data for two outputs from the two parallel input data and the delayed data, a control circuit (4) stopping a read clock signal of the elastic memory (1) for one clock period, and a pulse addition circuit (5) adding a pulse to the parallel data upon receipt of a pulse insertion request signal when the delayed data is selected or the read clock signal is stopped. By using this pulse insertion circuit, a pulse insertion necessary for multiplexing can be carried out with a circuitry adapted to operate at a half of a frequency of the series input data.
Inventors
- 👤 Naonobu Fujimoto
- 👤 Yukio Suda
- 👤 Katsutoshi Miyaji
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 06:32
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/07; H04J3/076
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
223 words
A pulse insertion circuit comprising: a series to parallel conversion means (6) for distributing series input data alternately and for converting said series input data to parallel data having a first input data and a second input data, a parallel type elastic memory (1) for receiving the first input data and the second input data which are written and read synchronously, a delay means (2) for receiving the second input data read from the elastic memory and for outputting data delayed by one bit, a selection means (3) for receiving the first input data and the second input data read from the elastic memory (1) by a read clock signal and the delayed data, for selecting one of the second input data and the delayed data, and for further selecting one of a cross and a no cross of the prior selected one of the second input data and the delayed data and the first input data, a control means (4) for stopping the read clock signal of the elastic memory (1) for one period upon receipt of a request for a pulse insertion, a pulse addition means (5) for adding a pulse when the output of the delay means (2) is selected by the selection means (3) and the clock is stopped for one period in response to the pulse insertion request.
Claim 2
Dependent Claim
223 words
A pulse insertion circuit comprising: a series to parallel conversion means (6) for distributing series input data alternately and for converting said series input data to parallel data having a first input data and a second input data, a parallel type elastic memory (1) for receiving the first input data and the second input data which are written and read synchronously, a delay means (2) for receiving the second input data read from the elastic memory and for outputting data delayed by one bit, a selection means (3) for receiving the first input data and the second input data read from the elastic memory (1) by a read clock signal and the delayed data, for selecting one of the second input data and the delayed data, and for further selecting one of a cross and a no cross of the prior selected one of the second input data and the delayed data and the first input data, a control means (4) for stopping the read clock signal of the elastic memory (1) for one period upon receipt of a request for a pulse insertion, a pulse addition means (5) for adding a pulse when the output of the delay means (2) is selected by the selection means (3) and the clock is stopped for one period in response to the pulse insertion request.
Claim 3
Dependent Claim
60 words
A pulse insertion circuit as set forth in claim 1, wherein the delay means (2) comprises a D type flip-flop (21), a D input terminal thereof receiving the second input data from the elastic memory (1), a clock input terminal thereof receiving the read clock for the elastic memory (1), and the delayed data being obtained at the output thereof.
Claim 4
Dependent Claim
143 words
A pulse insertion circuit as set forth in claim 1, wherein the selection means (3) receives a selection signal, and when the selection signal becomes "1", the first input data from the elastic memory (1) is supplied to a first output of the selection means (3) and the second input data from the elastic memory (1) is supplied to a second output of the selection means (3), and when the selection signal becomes "0", the output of the delay means (2) is supplied to the first output and the first input data is supplied to the second output, and the selection signal is inverted by an output of an exclusive OR circuit (25), the exclusive OR circuit (25) being supplied with a pulse insertion request signal for the first output and a one bit delayed pulse insertion request signal for the second output.
Claim 5
Dependent Claim
29 words
A pulse insertion circuit as set forth in claim 3, wherein only the pulse insertion request signal for the first output is supplied to the exclusive OR circuit (25).
Claim 6
Dependent Claim
42 words
A pulse insertion circuit as set forth in claim 3, wherein first the pulse insertion request signal for the first output is supplied and then the pulse insertion request signal for the second output is supplied, to the exclusive OR circuit (25).
Claim 7
Dependent Claim
42 words
A pulse insertion circuit as set forth in claim 3, wherein first the pulse insertion request signal for the second output is supplied and then the pulse insertion request signal for the first output is supplied, to the exclusive OR circuit (25).
Claim 8
Dependent Claim
29 words
A pulse insertion circuit as set forth in claim 3, wherein only the pulse insertion request signal for the second output is supplied to the exclusive OR circuit (25).
Claim 9
Dependent Claim
75 words
A pulse insertion circuit as set forth in claim 1, wherein the control means (4) for stopping the read clock signal for the elastic memory (1) for one period upon receipt of the pulse insertion request, stops the read clock signal for one period through an AND circuit (28) which receives a signal inverted by the read clock signal upon receipt of the pulse insertion request signal and receives the pulse insertion request signal also.
Claim 10
Dependent Claim
66 words
A pulse insertion circuit as set forth in claim 1, wherein the series to parallel conversion means (6) distributes the series input data alternately by a series input data clock signal to the first input data and the second input data delayed by one bit, subsequently delays the first input data by one bit, and obtains synchronized parallel data comprising the first and second input data.
References Cited (Backward Citations)
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