Patent EP0332135A2 successfully refreshed from Google Patents.
EP0332135A2
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EP
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Nonvolatile memory circuit device with low power consumption and wide operating voltage range
Assignee: Toshiba Corp
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Filing: 1989-03-07
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Granted: —
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Expires: 2009-03-07
Abstract
Abstract A column decoder (9) is driven by an intermediate potential VDD from a circuit (8) for generating an intermediate potential between a Vcc potential and a Vss potential, and a column selection output having a swing width (VDD-Vss) of the intermediate potential is supplied to the gates of column selection transistors (2) to limit a current flowing therethrough. In the data readout mode, a precharge potential generated from a dummy cell circuit (13) acting as a reference potential generating circuit according to a precharging signal supplied thereto is compared with a logic level of "1" or "0" read out according to the memory content by means of a flip-flop (12) acting as a sense amplifier, thus deriving a data readout output.
Inventors
- 👤 Makoto C/O Patent Division Ito
- 👤 Nobutaka C/O Patent Division Kitagawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 16:10
CPC Classifications
G; G11; G11C; G11C11/00; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
153 words
A nonvolatile memory circuit device characterized by comprising: a memory cell array having a plurality of memory cells (6) formed of nonvolatile transistors; a plurality of column lines (3) connected to drains of said memory cells (6); a plurality of column selection transistors (2) respectively connected at one end to said column lines (3) and commonly connected at the other end to a first node (A); a precharging transistor (1) of a first conductivity type connected between a first potential terminal (Vcc) and said first node (A); at least one discharging transistor (7) of a second conductivity type connected between a second potential terminal (Vss) and sources of said memory cells (6); potential supplying means (8) for selectively supplying a potential lower than the first potential at said first potential terminal to gates of said column selection transistors (2) according to address input; and a sense amplifier (10) connected to said first node.
Claim 2
Dependent Claim
153 words
A nonvolatile memory circuit device characterized by comprising: a memory cell array having a plurality of memory cells (6) formed of nonvolatile transistors; a plurality of column lines (3) connected to drains of said memory cells (6); a plurality of column selection transistors (2) respectively connected at one end to said column lines (3) and commonly connected at the other end to a first node (A); a precharging transistor (1) of a first conductivity type connected between a first potential terminal (Vcc) and said first node (A); at least one discharging transistor (7) of a second conductivity type connected between a second potential terminal (Vss) and sources of said memory cells (6); potential supplying means (8) for selectively supplying a potential lower than the first potential at said first potential terminal to gates of said column selection transistors (2) according to address input; and a sense amplifier (10) connected to said first node.
Claim 3
Dependent Claim
41 words
A nonvolatile memory circuit device according to claim 1, characterized in that said sense amplifier (10) includes a flip-flop formed of CMOS logic gate circuit (11, 12) for comparing the potential at said first node (A) with a reference potential (Vref).
Claim 4
Dependent Claim
165 words
A nonvolatile memory circuit device characterized by comprising: a memory cell array having a plurality of memory cells (6) formed of nonvolatile transistors; a plurality of column lines (3) connected to drains of said memory cells (6); a plurality of column selection transistors (2) respectively connected at one end to said column lines (3) and commonly connected at the other end to a first node (A); a precharging transistor (1) of a first conductivity type connected between a first potential terminal (Vcc) and a second node (C); at least one discharging transistor (7) of a second conductivity type connected between a second potential terminal (Vss) and sources of said memory cells (6); a level-down transistor (18) of the second conductivity type which is connected between said first and second nodes (A, C) and whose gate is supplied with a potential lower than the potential at said first potential terminal in the data readout mode; and a sense amplifier (10) connected to said second node (C).
Claim 5
Dependent Claim
165 words
A nonvolatile memory circuit device characterized by comprising: a memory cell array having a plurality of memory cells (6) formed of nonvolatile transistors; a plurality of column lines (3) connected to drains of said memory cells (6); a plurality of column selection transistors (2) respectively connected at one end to said column lines (3) and commonly connected at the other end to a first node (A); a precharging transistor (1) of a first conductivity type connected between a first potential terminal (Vcc) and a second node (C); at least one discharging transistor (7) of a second conductivity type connected between a second potential terminal (Vss) and sources of said memory cells (6); a level-down transistor (18) of the second conductivity type which is connected between said first and second nodes (A, C) and whose gate is supplied with a potential lower than the potential at said first potential terminal in the data readout mode; and a sense amplifier (10) connected to said second node (C).
Claim 6
Dependent Claim
44 words
A nonvolatile memory circuit device according to claim 3, characterized in that said sense amplifier (10) includes comparator means having a flip-flop formed of CMOS logic gate circuit (11, 12) for comparing the potential at said second node (C) with a reference potential (Vref).
Claim 7
Dependent Claim
55 words
A nonvolatile memory circuit device according to claim 1, characterized in that said device further comprises a power source terminal (Vcc), and said potential supplying means includes a constant potential circuit (25-27) for delivering said potential held at a constant value irrespective of a variation of an output voltage at said power source terminal (Vcc).
Claim 8
Dependent Claim
61 words
A nonvolatile memory circuit device according to claim 3, characterized in that said device further comprises a power source terminal (Vcc) and a potential supplying means (25-27) connected to said power source terminal (Vcc), said potential supplying means (25-27) supplying said potential held at a constant value irrespective of a variation of an output voltage at said power source terminal (Vcc).
References Cited (Backward Citations)
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