Eprom programming elements

Claim 2

An EPROM element (66) comprising a MOS transis­tor formed on a substrate (16) and comprising source (18) and drain (20) regions contacted by source (46s) and drain (46d) contacts, respectively, and a gate region (22) therebetween comprising a floating gate (40g) and a control gate (58), said control gate formed above said floating gate, said floating and control gates capacitively coupled together and separated from each other by a first dielectric (56) and from said source and drain contacts by a second dielectric (64), characterized by (a) mutual self-alignment of said source, gate, and drain regions, (b) said source and drain contacts and said control gate comprising verti­cally disposed conducting plugs, disposed in openings formed in insulating material (28) formed on said sub­strate, said openings defined by substantially perpen­dicular walls, said plugs terminating in upper connect­ing surfaces to form a coplanar surface in an area above said substrate and substantially parallel to said substrate for contacting by planar interconnects, (c) said plugs having a substantially identical width par­allel to said substrate, and (d) said plugs being ver­tically aligned with each other.

Claim 3

The EPROM element of Claim 1 wherein said MOS transistor comprises an N-channel device.

Claim 4

The EPROM element of Claim 1 wherein said first dielectric separating said floating and control gates comprises a material selected from the group consisting of (a) an oxide, ranging in thickness from about 100 to 200 Å; (b) an oxynitride about 100 Å thick; and (c) a first layer comprising an oxide about 80 Å thick and a second layer comprising a nitride about 100 Å thick.

Claim 5

The EPROM element of Claim 3 wherein in group (c), said second layer of silicon nitride is slightly oxidized to provide an oxide/nitride/oxide structure.

Claim 6

The EPROM element of Claim 1 wherein said source and drain contacts consist essentially of poly­silicon.

Claim 7

The EPROM element of Claim 1 wherein said source and drain contacts consist essentially of tung­sten.

Claim 8

The EPROM element of Claim 1 wherein a portion of said insulating material is of sufficient thickness to capacitively decouple said control gate from said substrate and wherein said second dielectric is of sufficient thickness to decouple said control gate from said source and drain contacts.

Claim 9

The EPROM element of Claim 1 wherein said con­trol gate is capacitively coupled to said floating gate both at the surface of said floating gate and around the periphery of said floating gate.

Claim 10

The EPROM element of Claim 8 wherein said first dielectric is substantially uniform in thickness.

Claim 11

A process for fabricating an EPROM element on a semiconductor substrate and employing self-aligning of source, gate and drain regions of a MOS transistor, comprising: (a) delineating an active area within which individual devices are made by forming an oxide region in said substrate therearound; (b) forming a multi-layer structure on said surface, said structure including a buried etch-stop layer sandwiched between dielectric layers; (c) using a mask in conjunction with a resist layer formed on said multi-layer structure and etching of undesired portions thereof to define a plurality of slots corresponding to said source, gate and drain components of said devices, thereby self-aligning said components with each other; (d) filling said slots with a conducting material and forming N regions in said substrate by implanting ions in regions underlying said slots; (e) removing upper portions of conducting material associated with said gate to form a floating gate comprising the remaining lower portion of said gate, the top surface of which is exposed; (f) forming an insulating layer over at least said exposed portion of said floating gate; (g) forming a control gate over said insulat­ing layer over said floating gate, capacitively coupled together; and (h) forming a metallic layer thereover to contact portions of said conducting material where contact is desired.

Claim 12

A process for fabricating an EPROM element on a semiconductor substrate and employing self-aligning of source, gate and drain regions of a MOS transistor, comprising: (a) delineating an active area within which individual devices are made by forming an oxide region in said substrate therearound; (b) forming a multi-layer structure on said surface, said structure including a buried etch-stop layer sandwiched between dielectric layers; (c) using a mask in conjunction with a resist layer formed on said multi-layer structure and etching of undesired portions thereof to define a plurality of slots corresponding to said source, gate and drain components of said devices, thereby self-aligning said components with each other; (d) filling said slots with a conducting material and forming N regions in said substrate by implanting ions in regions underlying said slots; (e) removing upper portions of conducting material associated with said gate to form a floating gate comprising the remaining lower portion of said gate, the top surface of which is exposed; (f) forming an insulating layer over at least said exposed portion of said floating gate; (g) forming a control gate over said insulat­ing layer over said floating gate, capacitively coupled together; and (h) forming a metallic layer thereover to contact portions of said conducting material where contact is desired.

Claim 13

The process of Claim 10 wherein after removing said upper portions of said conducting material of said gate, said control gate is formed by a process which includes removing insulating material between said source and said gate and between said drain and said gate down to said etch-stop layer, removing said etch-­stop layer to expose an underlying dielectric layer to leave an open region between said source and said drain, filling said open region with additional con­ducting material, and etching said additional conduct­ing material back to said plane of said conducting material.

Claim 14

The process of Claim 11 further including forming openings in said additional conducting material and filling said openings with an insulating material to electrically isolate said additional conducting material from said conducting material associated with said source and drain components.

Claim 15

The process of Claim 10 wherein said multi-­layer structure comprises: (a) a first layer consisting essentially of a field oxide; (b) a second layer consisting essentially of an etch-stop material having a significantly different etch rate than said field oxide; (c) a third layer consisting essentially of an oxide; and (d) a fourth layer consisting essentially of a material having an etch rate significantly different than said field oxide.

Claim 16

The process of Claim 13 wherein said fourth layer comprises a material selected from the group consisting of polysilicon and silicon nitride.

Claim 17

The process of Claim 10 wherein said conduct­ing material comprises a material selected from the group consisting of polysilicon and tungsten.

Claim 18

The process of Claim 15 wherein said conduct­ing material consists essentially of polysilicon and said slots are filled with said polysilicon and said N regions are formed in said substrate by implanting ions into said polysilicon in said slots.

Claim 19

The process of Claim 15 wherein said conduct­ing material consists essentially of tungsten and said N regions are formed in said substrate by implanting ions thereinto through said slots and said slots are 5 then filled with tungsten.

Claim 20

The process of Claim 10 wherein said dielec­tric separating said gate and said upper gate comprises a material selected from the group consisting of (a) an oxide, ranging in thickness from about 100 to 200 Å; (b) an oxynitride about 100 Å thick; and (c) a first layer comprising an oxide about 80 Å thick and a second layer comprising a nitride about 100 Å thick.

Claim 21

The process of Claim 18 wherein in group (c), said second layer of silicon nitride is slightly oxi­dized to provide an oxide/nitride/oxide structure.

Claim 22

A process for forming a self-aligned planar­ized EPROM element comprising source, gate, and drain components of a MOS transistor and formed in a major surface of a semiconductor, comprising: (a) delineating an active area within which individual devices are made by forming an oxide region in said substrate therearound; (b) forming a multi-layer structure on said semiconductor surface, said multi-layer structure in­cluding at least one etch-stop layer; (c) using a slot mask in conjunction with a resist layer formed on said multi-layer structure to lithographically define a plurality of slots corre­sponding to said source, gate, and drain components of said devices, thereby self-aligning said components with each other; (d) etching portions of said multi-layer structure corresponding to said slots, stopping at said etch-stop layer; (e) stripping said resist layer; (f) using an active mask in conjunction with another resist layer formed on said multi-layer struc­ture to define said active area encompassing a group of said slots associated with said active area of an indi­vidual device; (g) removing any remaining portions of said multi-layer structure in said slots; (h) filling said slots with a conducting material to form conducting plugs and forming N regions in said substrate by implanting ions in regions un­derlying said slots; (i) planarizing said plugs to the surface of said multi-layer structure; (j) removing upper portions of conducting material associated with said gate to form a floating gate comprising the remaining lower portion of said gate, the top surface of which is exposed; (k) forming an insulating layer over at least said exposed portion of said floating gate; (l) forming a control gate over said insulat­ing layer over said floating gate, capacitively coupled together; and (m) forming a metallic layer thereover to contact portions of said conducting material where contact is desired.

Claim 23

A process for forming a self-aligned planar­ized EPROM element comprising source, gate, and drain components of a MOS transistor and formed in a major surface of a semiconductor, comprising: (a) delineating an active area within which individual devices are made by forming an oxide region in said substrate therearound; (b) forming a multi-layer structure on said semiconductor surface, said multi-layer structure in­cluding at least one etch-stop layer; (c) using a slot mask in conjunction with a resist layer formed on said multi-layer structure to lithographically define a plurality of slots corre­sponding to said source, gate, and drain components of said devices, thereby self-aligning said components with each other; (d) etching portions of said multi-layer structure corresponding to said slots, stopping at said etch-stop layer; (e) stripping said resist layer; (f) using an active mask in conjunction with another resist layer formed on said multi-layer struc­ture to define said active area encompassing a group of said slots associated with said active area of an indi­vidual device; (g) removing any remaining portions of said multi-layer structure in said slots; (h) filling said slots with a conducting material to form conducting plugs and forming N regions in said substrate by implanting ions in regions un­derlying said slots; (i) planarizing said plugs to the surface of said multi-layer structure; (j) removing upper portions of conducting material associated with said gate to form a floating gate comprising the remaining lower portion of said gate, the top surface of which is exposed; (k) forming an insulating layer over at least said exposed portion of said floating gate; (l) forming a control gate over said insulat­ing layer over said floating gate, capacitively coupled together; and (m) forming a metallic layer thereover to contact portions of said conducting material where contact is desired.

Claim 24

The process of Claim 20 wherein after removing said upper portions of said conducting material of said gate, said control gate is formed by a process which includes removing insulating material between said source and said gate and between said drain and said gate down to said etch-stop layer, removing said etch-­stop layer to expose an underlying dielectric layer to leave an open region between said source and said drain, filling said open region with additional con­ducting material, and etching said additional conduct­ing material back to said plane of said conducting material.

Claim 25

The process of Claim 21 further including forming openings in said additional conducting material and filling said openings with an insulating material to electrically isolate said additional conducting material from said conducting material associated with said source and drain components.

Claim 26

The process of Claim 20 wherein said multi-­layer structure comprises: (a) a first layer consisting essentially of a field oxide; (b) a second layer consisting essentially of an etch-stop material having a significantly different etch rate than said field oxide; (c) a third layer consisting essentially of an oxide; and (d) a fourth layer consisting essentially of a material having an etch rate significantly different than said field oxide.

Claim 27

The process of Claim 23 wherein said fourth layer comprises a material selected from the group consisting of polysilicon and silicon nitride.

Claim 28

The process of Claim 20 further including implanting dopant species through exposed portions of said field oxide layer to form channel regions between at least some of said components.

Claim 29

The process of Claim 20 wherein said conduct­ing material comprises a material selected from the group consisting of polysilicon and tungsten.

Claim 30

The process of Claim 26 wherein said conduct­ing material consists essentially of polysilicon and said slots are filled with said polysilicon and said N regions are formed in said substrate by implanting ions into said polysilicon in said slots.

Claim 31

The process of Claim 26 wherein said conduct­ing material consists essentially of tungsten and said N regions are formed in said substrate by implanting ions thereinto through said slots and said slots are then filled with tungsten.

Claim 32

The process of Claim 20 wherein said dielec­tric separating said gate and said upper gate comprises a material selected from the group consisting of (a) silicon dioxide, ranging in thickness from about 100 to 200 Å; (b) silicon oxynitride about 100 Å thick; and (c) a first layer comprising silicon oxide about 80 Å thick and a second layer comprising silicon nitride about 100 Å thick.

Claim 33

A process for forming a self-aligned planar­ized EPROM element using a buried etch stop wherein P-­wells are formed in a major surface of a semiconductor, and wherein source, gate, and drain components are to be formed, comprising: (a) delineating an active area within which individual devices are made by forming an oxide region in said substrate therearound; (b) forming a multi-layer structure on said semiconductor surface, said multi-layer structure com­prising (1) a first layer consisting essentially of a field oxide, (2) a second layer consisting essential­ly of an etch-stop material having a significantly different etch rate than said field oxide, (3) a third layer consisting essentially of an oxide, and (4) a fourth layer consisting essential­ly of polysilicon or silicon nitride; (c) using a slot mask in conjunction with a resist layer formed on said multi-layer structure to lithographically define a plurality of slots corre­sponding to said source, gate, and drain components of said devices, thereby self-aligning said components with each other; (d) etching portions of said fourth and third corresponding to said slots, stopping at said etch-stop layer; (e) stripping said resist layer; (f) using an active mask in conjunction with another resist layer formed on said multi-layer struc­ture to define only said active area encompassing a group of said slots associated with an individual de­vice; (g) removing any remaining portions of said etch-stop layer in said slots, along with said field oxide therein; (h) forming a thin oxide on the exposed por­tions of said semiconductor in said slots associated with said gates of said device; (i) filling said slots with polysilicon to form polysilicon plugs and planarizing to the surface of said multi-layer structure; (j) implanting dopant species into said poly­silicon-filled slots associated with said sources and drains of said device; (k) forming an anti-contact mask over said sources and drains; (l) removing upper portions of polysilicon associated with said gate to form a floating gate com­prising the remaining exposed portion of said gate, the top surface of which is exposed; (m) applying a connector mask to expose por­tions of said multi-layer structure between said source and said gate and between said drain and said gate; (n) etching exposed portions of said third layer back to said buried etch-stop layer; (o) etching exposed portions of said etch-­stop layer to said field oxide layer; (p) implanting dopant species through exposed portions of said field oxide layer to form channel regions between said source and said gate and between said drain and said gate and for simultaneously doping the gate polysilicon electrode either n- or p-type; (q) forming an inter-polysilicon dielectric layer over all exposed portions of said polysilicon; (r) depositing a layer of polysilicon every­where and polishing said layer back to be planar with the tops of said sources and drains; (s) defining portions of said polysilicon layer and etching openings therethrough down to said field oxide layer, said openings surrounding a central portion of said polysilicon layer above said floating gate polysilicon, thereby forming a control gate over said insulating layer over said floating gate, capaci­tively coupled together; (t) filling said openings with a dielectric material to isolate said upper polysilicon from said sources and drains; and (u) forming a metallic layer thereover to contact portions of said polysilicon where contact is desired.

Claim 34

A process for forming a self-aligned planar­ized EPROM element using a buried etch stop wherein P-­wells are formed in a major surface of a semiconductor, and wherein source, gate, and drain components are to be formed, comprising: (a) delineating an active area within which individual devices are made by forming an oxide region in said substrate therearound; (b) forming a multi-layer structure on said semiconductor surface, said multi-layer structure com­prising (1) a first layer consisting essentially of a field oxide, (2) a second layer consisting essential­ly of an etch-stop material having a significantly different etch rate than said field oxide, (3) a third layer consisting essentially of an oxide, and (4) a fourth layer consisting essential­ly of polysilicon or silicon nitride; (c) using a slot mask in conjunction with a resist layer formed on said multi-layer structure to lithographically define a plurality of slots corre­sponding to said source, gate, and drain components of said devices, thereby self-aligning said components with each other; (d) etching portions of said fourth and third corresponding to said slots, stopping at said etch-stop layer; (e) stripping said resist layer; (f) using an active mask in conjunction with another resist layer formed on said multi-layer struc­ture to define only said active area encompassing a group of said slots associated with an individual de­vice; (g) removing any remaining portions of said etch-stop layer in said slots, along with said field oxide therein; (h) forming a thin oxide on the exposed por­tions of said semiconductor in said slots associated with said gates of said device; (i) filling said slots with polysilicon to form polysilicon plugs and planarizing to the surface of said multi-layer structure; (j) implanting dopant species into said poly­silicon-filled slots associated with said sources and drains of said device; (k) forming an anti-contact mask over said sources and drains; (l) removing upper portions of polysilicon associated with said gate to form a floating gate com­prising the remaining exposed portion of said gate, the top surface of which is exposed; (m) applying a connector mask to expose por­tions of said multi-layer structure between said source and said gate and between said drain and said gate; (n) etching exposed portions of said third layer back to said buried etch-stop layer; (o) etching exposed portions of said etch-­stop layer to said field oxide layer; (p) implanting dopant species through exposed portions of said field oxide layer to form channel regions between said source and said gate and between said drain and said gate and for simultaneously doping the gate polysilicon electrode either n- or p-type; (q) forming an inter-polysilicon dielectric layer over all exposed portions of said polysilicon; (r) depositing a layer of polysilicon every­where and polishing said layer back to be planar with the tops of said sources and drains; (s) defining portions of said polysilicon layer and etching openings therethrough down to said field oxide layer, said openings surrounding a central portion of said polysilicon layer above said floating gate polysilicon, thereby forming a control gate over said insulating layer over said floating gate, capaci­tively coupled together; (t) filling said openings with a dielectric material to isolate said upper polysilicon from said sources and drains; and (u) forming a metallic layer thereover to contact portions of said polysilicon where contact is desired.

Claim 35

The process of Claim 30 wherein said dielec­tric separating said gate and said upper gate comprises a material selected from the group consisting of (a) silicon dioxide, ranging in thickness from about 100 to 200 Å; (b) silicon oxynitride about 100 Å thick; and (c) a first layer comprising silicon oxide about 80 Å thick and a second layer comprising silicon nitride about 100 Å thick.

Claim 36

The process of Claim 31 wherein in group (c), said second layer of silicon nitride is slightly oxi­dized to provide an oxide/nitride/oxide structure.