Method of and apparatus using floating point execption signals for controlling several processors

Claim 3

A method as claimed in claim 1, wherein the data processing system is operable to execute instructions in a pipeline configuration in which plural instructions are in various stages of execution, the method including the step of: responding to the generation of the prediction signal by temporarily halting all other operations until completion of the floating point computation.

Claim 4

A method as claimed in claim 2 including the steps of: generating an interrupt signal at the completion fo the floating point computation if a floating point exception results; handling the floating point exception; and resuming the all other operations by accessing for execution the next instructions immediately following the floating point instructions.

Claim 7

A method as claimed in claim 4 including the steps of: generating an interrupt signal when the completion of the computation results in a floating point exception; resuming operation of the other processor unit in response to the interrupt to handle the floating point exception by, in part, adjusting the floating point operands causing the exception; and re-executing the floating point computation with the adjusted floating point operands.

Claim 8

A data processing system operable to perform floating point computations on at least first and second operands, each having an exponent field and a fractional field, the system comprising means for predicting floating point exceptions comprising: means for comparing the combination of exponent fields of the first and second operands to a predetermined criteria formed from the computation to be performed; means for generating an exception prediction signal to indicate that the performance of the operation is likely to cause a floating point exception.

Claim 9

A data processing system operable to perform floating point computations on at least first and second operands, each having an exponent field and a fractional field, the system comprising means for predicting floating point exceptions comprising: means for comparing the combination of exponent fields of the first and second operands to a predetermined criteria formed from the computation to be performed; means for generating an exception prediction signal to indicate that the performance of the operation is likely to cause a floating point exception.

Claim 10

A data processing system having pipelined architecture in which instructions are decoded and executed in stages, the system comprising: a computational unit operable in response to floating point instructions to conduct floating point computations involving at least two operands, each operand having an exponent field and a fractional field, and apparatus for predicting floating point exceptions for floating point add, subtract, multiply, and divide operations comprising: means for comparing the exponent fields of the two operands to criteria determined by the floating point operation to be performed on the operands to generate therefrom a prediction signal indicative of the possibility of the floating point exception occurring; means responsive to the prediction signal for stalling operation of the data processing system until completion of the floating point operation; means for generating an interrupt signal at the completion of the computation when a floating point exception has occurred; and means for handling the floating point exception and resuming operation of the data processing system with re-execution of the floating point instruction.

Claim 11

A data processing system having pipelined architecture in which instructions are decoded and executed in stages, the system comprising: a computational unit operable in response to floating point instructions to conduct floating point computations involving at least two operands, each operand having an exponent field and a fractional field, and apparatus for predicting floating point exceptions for floating point add, subtract, multiply, and divide operations comprising: means for comparing the exponent fields of the two operands to criteria determined by the floating point operation to be performed on the operands to generate therefrom a prediction signal indicative of the possibility of the floating point exception occurring; means responsive to the prediction signal for stalling operation of the data processing system until completion of the floating point operation; means for generating an interrupt signal at the completion of the computation when a floating point exception has occurred; and means for handling the floating point exception and resuming operation of the data processing system with re-execution of the floating point instruction.

Claim 12

A data processing system comprising: at least a pair of processor units, a one of processor units being operable to perform floating point computations on first and second operands, each having an exponent field and a fractional field, the other processor unit being operable to perform other data processing tasks in parallel with floating pint computations, and apparatus for handling floating point operation exceptions comprising: in the one processor unit, first circuit means for comparing the floating point operands to first predetermined criteria for add, subtract, and unary computations and for generating a first signal when the comparison indicates the possibility of a floating point exception occurring; second circuit means for comparing the combination of the exponent fields of the first and the second operands to second predetermined criteria for floating point multiply and divide computations and for generating a second signal when the comparison indicates the possibility of a floating point exception occurring; generating means for providing a floating point exception prediction signal when the first or the second signals are present; and means in the other processor unit for halting operation in response to and during occurrence of the floating point exception prediction signal.

Claim 13

A data processing system comprising: at least a pair of processor units, a one of processor units being operable to perform floating point computations on first and second operands, each having an exponent field and a fractional field, the other processor unit being operable to perform other data processing tasks in parallel with floating pint computations, and apparatus for handling floating point operation exceptions comprising: in the one processor unit, first circuit means for comparing the floating point operands to first predetermined criteria for add, subtract, and unary computations and for generating a first signal when the comparison indicates the possibility of a floating point exception occurring; second circuit means for comparing the combination of the exponent fields of the first and the second operands to second predetermined criteria for floating point multiply and divide computations and for generating a second signal when the comparison indicates the possibility of a floating point exception occurring; generating means for providing a floating point exception prediction signal when the first or the second signals are present; and means in the other processor unit for halting operation in response to and during occurrence of the floating point exception prediction signal.

Claim 14

A data processing system as claimed in claim 8 including means for generating an interrupt signal at completion of the floating point computation when the computation results in a floating point exception; and means for handling the exception.

Claim 15

A method as claimed in claim 9 wherein the means for handling the exception includes means for adjusting the operands, and means for resuming operation of the other processor unit with a floating point computation using the adjusted operands.