Logic circuit with a test function

Claim 2

A logic circuit which as a testing function for test execution and a function for normal mode operation, comprising: macrocell means (2) having input-output circuit means (8) for, in the test execution for the macrocell means (2), inputting a test input data and outputting a test output data, including first holding means (12,14) for holding the test data; selector circuit means (15) for shutting off an input path of normal mode operation signals to the macrocell means (2) in the test execution for the macrocell means (2), selecting the test input data held in the first holding means (12,14), and outputting the test input data to a test object portion of the macrocell means (2); second holding means (18) for holding the test output data obtained as a result of the test execution for the macrocell means (2) on the test input data and supplied from the test object portion of the macrocell means (2), and outputting the test output data to the outside of the macrocell means (2); and switching circuit means (19) for shutting off, in the test execution for the macrocell means (2), an output path of normal mode operation signals from the macrocell means (2) to other circuit portions of the logic circuit, whereby each macrocell (2) in the logic circuit can be tested independently.

Claim 3

The logic circuit of claim 1, wherein the first and the second holding means (12,14,18) include a shift register (12,14,18), respectively.

Claim 4

The logic circuit of claim 1, which further comprises: decoder means (5) for receiving a select signal for selecting a macrocell means (2) to be tested, decoding the select signal, and supplying the decoded select signal to the input-output circuit means (8) of the macrocell means (2) to be tested.

Claim 5

The logic circuit of claim 1, which further comprises: input-output circuit means (8) for, in the test execution for the logic circuit, inputting the test input data and outputting the test output data, including first holding means (12,14) for holding the test input data; selector circuit means (15) for shutting off an input path of normal mode operation signals to the logic circuit in the test execution for the logic circuit, selecting the test input data held in the first holding means (12,14), and outputting the test input data to a test object portion of the logic circuit; second holding means (18) for holding the test output data obtained as a result of the test execution for the logic circuit on the test input data and supplied from the test object portion of the logic circuit, and outputting the test output data to the outside of the logic circuit; and switching circuit means (19) for shutting off, in the test execution for the logic circuit, an output path of normal mode operation signals from the logic circuit to the outside, whereby the logic circuit can be tested independently.

Claim 6

A logic circuit which has a testing function for test execution and a function for normal mode operation, comprising: macrocell means (2) having input-output circuit means (8) for, in the test execution for the macrocell means, inputting a test input data and outputting a test output data, including first holding means (12) for holding the test input data; second holding means (14) for holding the test input data transferred from the first holding means (12); selector circuit means (15) for shutting off an input path of normal mode operation signals to the macrocell means (12) in the test execution for the macrocell means (2), selecting the test input data held in the second holding means (14), and outputting the test input data to a test object portion of the macrocell .means (2); third holding means (18) for holding the test output data obtained as a result of the test execution for the macrocell means (2) on the test input data and supplied from the test object portion of the macrocell means (2), and outputting the test output data to the outside of the macrocell means (2); and switching circuit means (19) for shutting off, in the test execution for the macrocell means (2), an output path of normal mode operation signals from the macrocell means (2) to other circuit portions of the logic circuit, whereby each macrocell (2) in the logic circuit can be tested independently.

Claim 7

A logic circuit which has a testing function for test execution and a function for normal mode operation, comprising: macrocell means (2) having input-output circuit means (8) for, in the test execution for the macrocell means, inputting a test input data and outputting a test output data, including first holding means (12) for holding the test input data; second holding means (14) for holding the test input data transferred from the first holding means (12); selector circuit means (15) for shutting off an input path of normal mode operation signals to the macrocell means (12) in the test execution for the macrocell means (2), selecting the test input data held in the second holding means (14), and outputting the test input data to a test object portion of the macrocell .means (2); third holding means (18) for holding the test output data obtained as a result of the test execution for the macrocell means (2) on the test input data and supplied from the test object portion of the macrocell means (2), and outputting the test output data to the outside of the macrocell means (2); and switching circuit means (19) for shutting off, in the test execution for the macrocell means (2), an output path of normal mode operation signals from the macrocell means (2) to other circuit portions of the logic circuit, whereby each macrocell (2) in the logic circuit can be tested independently.

Claim 8

The logic circuit of claim 5, wherein the first and second holding means (12,14) include a shift register (12,14) respectively, and the shift register (14) constituting the second holding means (14) is connected to the shift register (18) constituting the third holding means (18) in series to output the test output data as well as the test input data.

Claim 9

The logic circuit of claim 5, wherein the first and third holding means (12,14,18) include a shift register (12,14,18), respectively.

Claim 10

The logic circuit of claim 5, which further comprises: decoder means (5) for receiving a select signal for selecting a macrocell means (2) to be tested, decoding the select signal, and supplying the decoded select signal to the input-output circuit means (8) of the macrocell means (2) to be tested.