Sampled data subsampling apparatus

Claim 2

Apparatus for filtering a sampled data signal, including an accumulator comprising: a sampled data input port (50) for receiving said sampled data signal, and a serial output port (70); and characterized by a plurality of adder circuits each having carry-­input (CI), carry-output (CO), addend input (A), augend input (B) and sum data terminals (DO), and including means (77,78) for selectively coupling said sum data terminal (DO) or a reference value to said augend input terminal (B); means (70) for connecting N, an integer, of said adder circuits in parallel wherein said adder circuits (520,521,522,523,524,525) are ordinally numbered one to N, the carry input terminal of adder circuit numbered one being coupled to a reference value and the carry output terminal of each adder circuit being connected to the carry-input terminal of the next higher ordinally numbered adder circuit, the addend input (A) terminal of at least adder circuit numbered one being coupled to said sampled data input port (50), and the addend input terminals of adder circuits which are not coupled to said sampled data input port being coupled to a reference value; and means (59) for successively coupling in the order of ordinal numbering of adder circuits, the respective sum data terminals to said serial output port.

Claim 3

Apparatus as set forth in Claim 1 characterized in that said accumulator further includes means for connecting M of said adder circuits (530,531,532,533,534,535,536,537,538,539) in parallel, M an integer greater than N, wherein said M adder circuits are ordinally numbered one to M, the carry input connection of adder circuit numbered one being coupled to a reference value and the carry output connection of each adder circuit being connected to the carry input connection of the next higher ordinally numbered adder circuit, the addend input connections of the first N of the M parallel connected adder circuits being coupled to the sum data terminals (DO) of the N parallel connected adder circuits according to their corresponding ordinal numbering, the addend input connections of the remaining M parallel connected adder circuits which are not connected to the sum data output terminals of the N parallel connected adder circuits being respectively connected to a reference value; a further serial output port (72); and said means (59) successively coupling in the order of ordinal numbering of adder circuits, the respective sum data terminals to said further serial output port.

Claim 4

Apparatus as set forth in Claim 1, further characterized by each of said adder circuits being a one-bit adder having carry-input, carry-output, addend input, augend input, data output, strobe (S) and strobed data output terminals (SDO), said adder providing a carry output signal to said carry output terminal and a sum output signal to said data output terminals, which carry output and sum output signals are delayed by one input sample period relative to samples applied to inputs of said full adder, said adder circuit further including first (79) and second (78) gating means having respective control input c onnections coupled to said strobe input terminal, and having respective input terminals coupled to receive said delayed sum output signal, said first gating means (79) coupling said delayed sum output signal to said strobed data output terminal responsive to a first state of a strobe signal and exhibiting high impedance responsive to a second state of said strobe signal, said second gating means (78) coupling said delayed sum signal to said augend input terminal responsive to said second state of said strobe signal and coupling a zero value to said augend input terminal responsive to said first state of said strobe signal; the strobed data output terminals (SDO) being coupled to a first common output bus (70), and said means (59) generating a plurality of bistate signals, coupled to respective strobe input terminals of said adder circuits for successively strobing said adder circuits in ascending order of their ordinal numbering.

Claim 5

Apparatus as set forth in Claim 3 characterized in that said accumulator further includes means for connecting M of said adder circuits in parallel, M an integer greater than N, wherein said M adder circuits are ordinally numbered one to M, the carry input terminal of adder circuit numbered one being coupled to a logical zero value and the carry output terminal of each adder circuit being connected to the carry input terminal of the next higher ordinally numbered adder circuit, the strobed data output terminals being coupled to a second common output bus, the addend input terminals of the first N of the M parallel connected adder circuits being coupled to the data output terminals of the N parallel connected adder circuits according to their corresponding ordinal numbering, the addend input terminals of the remaining M parallel connected adder circuits which are not connected to the data output terminals of the N parallel connected adder circuits being respectively connected to a logical zero value, and means (P2,P3,P4,P5,P6,P7,P8,P9,P10,P11) for coupling the strobe terminals (S) of said M parallel connected adder circuits to said means (59) for generating a plurality of bi-state signals such that said M parallel connected adder circuits are strobed in ascending order of their ordinal numbering.