Operation mode setting circuit for DRAM

Claim 2

An operation mode setting circuit for setting the operation of a dynamic random access memory charac­terized by comprising: first means (13) for converting the level of a mode setting signal ( WE ) supplied from the exterior; second means (14) for converting the level of a column address strobe signal ( CAS ); mode selection means (15) for latching and outputting a mode selection signal based on latched output signals of said first and second means (13 and 14) in response to a row address strobe signal ( RAS ); latching means (16) for receiving an address signal supplied from the exterior and an internally formed address signal, latching one of the received address signals in response to the mode selection signal from said mode selection means (15) and the row address strobe signal ( RAS ), and outputting the latched signal to word line selection means (17) for selecting the word line of a dynamic random access memory; and control signal generation means (18) for generating control signals ( HLD , ACP, ALTC , NAC, REF) for controlling the operation of said latching means (16) based on the row address strobe signal ( RAS ) and auto-refresh signal (AR).

Claim 3

An operation mode setting circuit according to claim 1, characterized in that the mode setting signal ( WE ) is set up before the row address strobe signal ( RAS ) is activated, in a case where a mode other than the auto-refresh mode is specified in an operation mode in which the column address strobe signal ( CAS ) is acti­vated before the row address strobe signal ( RAS ), the set-up allowance time (t S ) with respect to the activa­tion timing of the row address strobe signal ( RAS ) is set to be larger than the minimum value (t ASRmin ) of the set-up allowance time (t ASR ) of the external address signal, the mode setting signal ( WE ) is latched by said mode selection means (15) at the time of activation of the row address strobe signal ( RAS ) and the latched signal is used to select and control the operation mode.

Claim 4

An operation mode setting circuit according to claim 1, characterized in that the set-up time (t CSR ) of the column address strobe signal ( CAS ) with respect to the row address strobe signal ( RAS ) is set to be larger than the minimum value (t ASRmin ) of the set-up time (t ASR ) of the external address signal, and the minimum value (t Smin ) of the set-up time (t S ) of the externally supplied mode setting signal ( WE ) is set to be equal to the minimum value (t CSRmin ) of the set-up time (t CSR ) of the column address strobe signal ( CAS ) with respect to the row address strobe signal ( RAS ).

Claim 5

An operation mode setting circuit according to claim 1, characterized in that the set-up time (t CSR ) of the column address signal ( CAS ) with respect to the row address strobe signal ( RAS ) is set to be larger than the minimum value (t ASRmin ) of the set-up time (t ASR ) of the external address signal, and the minimum value (t Smin ) of the set-up time (t S ) of the externally supplied mode setting signal ( WE ) is set to be larger than the minimum value (t ASRmin ) of the set-up time (t ASR ) of the exter­nal address signal.

Claim 6

An operation mode setting circuit according to claim 1, characterized in that the externally supplied mode setting signal includes at least one of write enable signal ( WE ) and output enable signal ( OE ).

Claim 7

An operation mode setting circuit according to claim 1, characterized in that each of said first and second means (13 and 14) for converting the level of the mode setting signal includes a level conversion circuit (19) for converting the level of an input signal to be CMOS logic level and an inverter (27) for forming a complementary signal based on the output signal of said level conversion circuit (19).

Claim 8

An operation mode setting circuit according to claim 6, characterized in that said level conversion circuit (19) includes a first MOS transistor (20) of a first conductivity type having a current path which is connected at one end to a first potential supplying source (V DD ) and a gate connected to a second potential supplying source; a second MOS transistor (21) of the first conductivity type having a current path which is connected at one end to the other end of the current path of said first MOS transistor (20) and a gate con­nected to receive a mode setting signal ( CAS , WE , OE ); a third MOS transistor (22) of a second conductivity type having a current path which is connected at one end to the other end of the current path of said second MOS transistor (21) and a gate connected to receive the mode setting signal ( CAS , WE , OE ); a fourth MOS transistor (23) of the second conductivity type having a current path connected between the other end of the current path of said third MOS transistor (22) and said second poten­tial supplying source and a gate connected to receive a mode setting signal ( CAS , WE , OE ); a first inverter (25) having an input terminal connected to a connection node between said second and third MOS transistors (21 and 22); a fifth MOS transistor (24) of the second conduc­tivity type having a current path connected at one end to the connection node between said second and third MOS transistors (21 and 22) and connected at the other end to a connection node between said third and fourth MOS transistors (22 and 23) and a gate connected to the out­put terminal of said first inverter (25); and a second inverter (26) having an input terminal connected to the output terminal of said first inverter (25).

Claim 9

An operation mode setting circuit according to claim 1, characterized in that said mode setting means (15) includes a first NAND gate (28) connected to receive output signals (CIN, WIN, OIN) of said first and second means (13 and 14) for converting the level of the mode setting signal; a first inverter (30) having an input terminal connected to receive a latch signal (LTC); a second NAND gate (29) having a first input ter­minal connected to the output terminal of said first NAND gate (28) and a second input terminal connected to the output terminal of said first inverter (30); a first MOS transistor (31) of a first conductivity type having a current path which is connected at one end to a first potential supplying source (V DD ) and a gate connected to the output terminal of said second NAND gate (29); a second MOS transistor (32) of a second conductivity type having a current path which is connected at one end to the other end of the current path of said first MOS transistor (31) and a gate connected to the output ter­minal of said second NAND gate (29); a third MOS tran­sistor (34) of the second conductivity type having a current path connected between the other end of the current path of said second MOS transistor (32) and a second potential supplying source, and a gate connected to the output terminal of said first inverter (30); a second inverter (36) having an input terminal connected to a connection node between said first and second MOS transistors (31 and 32); a fourth MOS transistor (35) of the second conductivity type having a current path which is connected at one end to a connection node between said second and third MOS transistors (32 and 34) and connected at the other end to said second potential supplying source, and a gate connected to the output terminal of said second inverter (36); and fifth and sixth MOS transistors (37 and 38) of the first conduc­tivity type having current paths connected in series between said first potential supplying source (V DD ) and the input terminal of said second inverter (36), the gate of one of said fifth and sixth MOS transistors (37 and 38) being connected to the output terminal of said second inverter (36) and the other gate being connected to the output terminal of said first inverter (30); and a mode selection signal (Ti) is derived from the output terminal of said second inverter (36).

Claim 10

An operation mode setting circuit according to claim 1, characterized in that said latching means includes an address buffer circuit (16).

Claim 11

An operation mode setting circuit according to claim 9, characterized in that said address buffer cir­cuit (16) includes an external address receiving section and an address selecting section.

Claim 12

An operation mode setting circuit according to claim 10, characterized in that a one-bit processing circuit portion of said external address receiving sec­tion includes a first MOS transistor (55) of a first conductivity type having a current path connected at one end to a first potential supplying source (V DD ) and a gate connected to a second potential supplying source; a second MOS transistor (49) of a second conductivity type having a current path connected at one end to the other end of the current path of said first MOS transistor (55) and a gate connected to receive a first control signal (ACP) generated from said control signal generating means (18); a third MOS transistor (50) of the second conductivity type having a current path con­nected at one end to receive an external address signal and a gate connected to receive a second control signal ( HLD ) generated from said control signal generating means (18); a fourth MOS transistor (51) of the second conductivity type having a current path connected be­tween the other end of the current path of said second MPS transistor (49) and said second potential supplying source, and a gate connected to the other end of the current path of said third MOS transistor (50); a fifth MOS transistor (56) of the first conductivity type having a current path connected at one end to said first potential supplying source (V DD ) and a gate connected to said second potential supplying source; a sixth MOS transistor (52) of the second conductivity type having a current path connected at one end to the other end of the current path of said fifth MOS transistor (56) and a gate connected to receive the first control signal (ACP) generated from said control signal generating means (18); a seventh MOS transistor (53) of the second con­ductivity type having a current path connected at one end to receive a reference voltage (V REF ) and a gate connected to receive second control signal ( HLD ) gener­ated from said control signal generating means (18); an eighth MOS transistor (54) of the second conductivity type having a current path connected between the other end of the current path of said sixth MOS transistor (52) and said second potential supplying source, and a gate connected to the other end of the current path of said seventh MOS transistor (53); and a differential amplifier circuit (57) which has a first input terminal connected to a connection node between said first and second MOS transistors (55 and 49) and a second input terminal connected to a connection node between said fifth and sixth MOS transistors (56 and 52) and whose operation is controlled by a third control signal ( ALTC ) generated from said control signal generating means (18); and a first address signal ( A ) is derived from the connection node between said first and second MOS tran­sistors (55 and 49), and a second address signal (A) which is in the inverted form of the first address signal ( A ) is derived from the connection node between said fifth and sixth MOS transistors (56 and 52).

Claim 13

An operation mode setting circuit according to claim 11, characterized in that said differential amplifier circuit (57) includes a first inverter and a second inverter whose input and output terminals are respectively connected to the output and input terminals of said first inverter.

Claim 14

An operation mode setting circuit according to claim 10, characterized in that said address select­ing section includes first and second MOS transistors (58 and 59) each having a current path connected at one end to receive a corresponding output signal of said external address receiving section and a gate connected to receive a fourth control signal (NAC) generated from said control signal generating means (18); third and fourth MOS transistors (60 and 61) each having a current path connected at one end to receive a corresponding one of the internal address signals and a gate connected to receive a fifth control signal (REF) generated from said control signal generating means (18); a first latching circuit (62) having an input terminal connected to the other ends of the current paths of said first and third MOS transistors (58 and 60); a second latching circuit (63) having an input terminal connected to the other ends of the current paths of said second and fourth MOS transistors (59 and 61); and a pull-down circuit (64) connected between the output terminals of said first and second latching circuits (62 and 63); the output signals (B, B ) of said first and second latching circuits (62 and 63) are supplied to said word line selection means (17).

Claim 15

An operation mode setting circuit according to claim 13, characterized in that each of said first and second latching circuits (62 and 63) includes a first inverter and a second inverter whose input and output terminals are respectively connected to the out­put and input terminals of said first inverter.

Claim 16

An operation mode setting circuit according to claim 13, characterized in that said pull-down circuit (64) includes a first MOS transistor having a current path connected between the output terminal of said first latching circuit (62) and the ground terminal, and a gate connected to the output terminal of said second latching circuit (63); and a second MOS transistor having a current path connected between the output ter­minal of said second latching circuit (63) and the ground terminal, and a gate connected to the output ter­minal of said first latching circuit (62).

Claim 17

An operation mode setting circuit according to claim 1, characterized in that said control signal generating means (18) includes a first inverter (65) having an input terminal connected to receive a negative pulse signal generated in synchronism with the row address strobe signal ( RAS ); a second inverter (66) having an input terminal connected to the output ter­minal of said first inverter (65); a third inverter (67) having an input terminal connected to the output ter­minal of said first inverter (65); a fourth inverter (68) having an input terminal connected to the output terminal of said third inverter (67); a fifth inverter (69) having an input terminal connected to the output terminal of said fourth inverter (68); a sixth inverter (70) having an input terminal connected to receive the negative pulse signal; a NAND gate having a first input terminal connected to the output terminal of said sixth inverter (70) and a second input terminal connected to receive the auto-refresh signal (AR); a seventh inverter (72) having an input terminal connected to the output terminal of said NAND gate (71); a NOR gate (73) having a first input terminal connected to receive the negative pulse signal and a second input terminal connected to receive the auto-refresh signal (AR); an eighth inverter (74) having an input terminal connected to the output terminal of said NOR gate (73); and a ninth inverter (75) having an input terminal connected to the output terminal of said eighth inverter (74); and a first control signal (ACP) is derived from the output terminal of said first inverter (65), a second control a signal ( HLD ) is derived from the output terminal of said second inverter (66), a third control signal ( ALTC ) is derived from the output terminal of said fifth inverter (69), a fourth control signal (NAC) is derived from the output terminal of said ninth inverter (75), and a fifth control signal (REF) is derived from the output terminal of said seventh inverter (72).

Claim 18

An operation mode setting circuit according to claim 1, characterized in that said mode selection means (15) can accept data in a period during which the row address strobe signal ( RAS ) is set in the activated state and in a preset period of time after the row address strobe signal ( RAS ) has been set into the activated state; and said latching means (16) accepts one of the address signals when the row address strobe signal ( RAS ) is in the activated state, and interrupts the reception of the address signal after a predeter­mined period of time.