Gain control circuit for amplifier having stepwise variable gain

Claim 2

An amplifier circuit comprising an amplifier having a stepwise variable gain and amplifying an input voltage with a gain designated by a gain control data, means for detecting and holding a peak value of an output voltage derived from said amplifier, means for generating a first reference voltage and a second reference voltage having a value different from said first reference voltage, comparison means for comparing said peak value with said first and second reference voltages, control means responsive to a comparison output of said comparison means for controlling said gain control data such that said peak value becomes to intervene between said first and second reference voltages.

Claim 3

The circuit as claimed in claim 1, wherein a voltage difference between said first and second reference voltages is larger than a voltage change of said output voltage of when the gain of said amplifier is varied by one step.

Claim 4

The circuit as claimed in claim 2, wherein said voltage difference is smaller than a twice value of said voltage change.

Claim 5

The circuit as claimed in claim 1, wherein the value of said second reference voltage is higher than the value of said first reference voltage and said comparison means produces a first comparison output when said peak value is smaller than said first reference voltage, a second comparison output when said peak value is between said first and second reference voltages and a third comparison output when said peak value is higher than said second reference voltage, said control means changing the content of said gain control data such that the gain of said amplifier is increased in response to said first comparison output, holding the content of said gain control data in response to said second comparison output and changing the content of said gain control data such that the gain of said amplifier is decreased in response to said third comparison output.

Claim 6

The circuit as claimed in claim 4, wherein said comparison means includes a first comparator supplied with said peak value and said first reference voltage and a second comparator supplied with said peak value and said second reference voltage.

Claim 7

The circuit as claimed in claim 4, wherein said comparison means includes a comparator having a first terminal supplied said peak value and a second terminal supplied alternately with said first and second reference voltages.

Claim 8

A gain-controlled amplifier circuit comprising an amplifier, a control circuit controlling a gain of said amplifier, said amplifier amplifying an input voltage with the controlled gain to produce an output voltage, said control circuit including means responsive to first data for incrementing the gain of said amplifier one step by one step, means responsive to second data for holding the gain of said amplifier at a current value and means responsive to third data for decrementing the gain of said amplifier one step by one step, a detection circuit detecting an amplitude of said output voltage and producing a detected voltage responsive to the amplitude of said output voltage, a reference voltage generator generating a first reference voltage and a second reference voltage that is higher than said first reference voltage, and circuit means for comparing said detected voltage with said first and second reference voltages and for producing said first data when said detected voltage is smaller than said first reference voltage, said second data when said detected voltage intervenes between said first and second reference voltages and said third data when said detected voltage is higher than said second reference voltage.

Claim 9

A gain-controlled amplifier circuit comprising an amplifier, a control circuit controlling a gain of said amplifier, said amplifier amplifying an input voltage with the controlled gain to produce an output voltage, said control circuit including means responsive to first data for incrementing the gain of said amplifier one step by one step, means responsive to second data for holding the gain of said amplifier at a current value and means responsive to third data for decrementing the gain of said amplifier one step by one step, a detection circuit detecting an amplitude of said output voltage and producing a detected voltage responsive to the amplitude of said output voltage, a reference voltage generator generating a first reference voltage and a second reference voltage that is higher than said first reference voltage, and circuit means for comparing said detected voltage with said first and second reference voltages and for producing said first data when said detected voltage is smaller than said first reference voltage, said second data when said detected voltage intervenes between said first and second reference voltages and said third data when said detected voltage is higher than said second reference voltage.

Claim 10

The circuit as claimed in claim 7, wherein said control circuit controls the gain of said amplifier in synchronism with a first clock and said detection circuit detects the amplitude of said output voltage in synchronism with a second clock, said second clock having a clock rate higher than the clock rate of said first clock.

Claim 11

The circuit as claimed in claim 7, wherein said circuit means includes a first comparator comparing said detected voltage with said first reference v9ltage, a second comparator comparing said detected voltage with said second reference voltage and means responsive to outputs of said first and second comparators for producing one of said first, second and third data.

Claim 12

The circuit as claimed in claim 7, wherein said circuit means includes a comparator having first and second input nodes, means for supplying said detected voltage to said first input node, means for supplying said first reference voltage to said second input node in a first state, means for supplying said second reference voltage to said second input node in a second state, means activated in said first state for latching an output of said comparator, means activated in said second state for latching the output of said comparator, and means responsive to contents of said two latching means for producing one of said first, second and third data.