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Patent EP0324650A2 successfully refreshed from Google Patents.
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EP0324650A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Timing pulse generators

Assignee: Sony Corp
•
Filing: 1989-01-13
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Granted: —
•
Expires: 2009-01-13
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Abstract

Abstract A timing pulse generator (60) for generating at least a first timing pulse (SV1) with a vertical scanning frequency and a second timing pulse (SH1, SH2) with a horizontal scanning frequency, both of the first and second timing pulses being used for controlling a charge coupled device imager (1). The timing pulse generator (60) includes a vertical ROM arrangement (69) having a first address counter (691) for counting a first reference pulse (CLKV) having the horizontal scanning frequency, and a first ROM (692) supplied with the output of the first address counter as a read out address control signal and for generating the first timing pulse (SV1). A horizontal ROM arrangement (65) includes a second address counter (651,651',652') for counting a second reference pulse (CLKH) having a frequency sufficiently higher than that of the horizontal scanning frequency, and a second ROM (652, 653', 654') supplied with the output of the second address counter as a read out address control signal and for generating the second timing pulse (SH1, SH2). A clock signal generating circuit (68) generates clock signals (V1' to V4') in accordance with the first and second timing pulses (SV1, SH1, SH2).

Inventors

  • 👤 Masanori C/O Patents Division Yamaguchi
  • 👤 Maki C/O Patents Division Sato

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-09 18:07
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/02; G06F1/025; H; H04; H04N; H04N25/00; H04N25/70; H04N25/71; H04N25/745

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 188 words
A timing pulse generator for generating at least a first timing pulse (SV1) with a vertical scanning frequency and a second timing pulse (P1, P2) with a horizontal scanning frequency (fH), both of said first and second timing pulses (SV1, P1, P2) being used for controlling a charge coupled device imager (1), said timing pulse generator (60) comprising: a first address counter (691) for counting a first reference pulse (CLKV) having the horizontal scanning frequency (fH); first read only memory means (692) supplied with the output of said first address counter (691) as a read out address control signal and for generating said first timing pulse (SV1); a second address counter (651) for counting a second reference pulse (CLKH) having a frequency higher than that of said horizontal scanning frequency (fH); second read only memory means (652) supplied with the output of said second address counter (651) as a read out address control signal and for generating said second timing pulse (P1, P2); and clock signal generating means (68) for generating clock signals (V1′ to V4′) in accordance with said first and second timing pulses (SV1, P1, P2).
Claim 2
Dependent Claim 188 words
A timing pulse generator for generating at least a first timing pulse (SV1) with a vertical scanning frequency and a second timing pulse (P1, P2) with a horizontal scanning frequency (fH), both of said first and second timing pulses (SV1, P1, P2) being used for controlling a charge coupled device imager (1), said timing pulse generator (60) comprising: a first address counter (691) for counting a first reference pulse (CLKV) having the horizontal scanning frequency (fH); first read only memory means (692) supplied with the output of said first address counter (691) as a read out address control signal and for generating said first timing pulse (SV1); a second address counter (651) for counting a second reference pulse (CLKH) having a frequency higher than that of said horizontal scanning frequency (fH); second read only memory means (652) supplied with the output of said second address counter (651) as a read out address control signal and for generating said second timing pulse (P1, P2); and clock signal generating means (68) for generating clock signals (V1′ to V4′) in accordance with said first and second timing pulses (SV1, P1, P2).
Claim 3
Dependent Claim 135 words
A timing pulse generator according to claim 1, wherein said second read only memory means includes a first read only memory (654′) storing logical level data and a second read only memory (653′) storing pulse duration data, the output of said first read only memory (654′) being operable to generate said second timing pulse (P1, P2), and said second address counter includes a first counter (651′) for counting said second reference pulse (CLKH) and for generating an output when the counted value thereof becomes a predetermined relation with the output (DCK) of said second read only memory (653′) and a second counter (652′) controlled by the output of said first counter (651′), the output of said second counter (652′) being operable to control the address of said first and second read only memories (654′, 653′).

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