Interconnect system for multiprocessor structure

Claim 2

Digital data processing apparatus comprising A. bus means for transferring information-­representative digital signals, said bus means including shift register means having a set of digital storage and transfer stages connected in series, for sequentially storing and transferring said information-­representative digital signals, and B. a plurality of processing cells, connected in a ring configuration to said bus means, at least one of said cells including any of (1) a central processing unit, (ii) an associated memory element for storing information-representative digital signals, coupled with said central processing unit for information transfer therebetween, and (iii)associated cell interconnect means, connected in circuit with said shift register means, and with an associated central processing unit, for transferring information-representative signals onto said shift register means.

Claim 3

Digital data processing apparatus as claimed in claim 1, characterised in that said bus means comprises unidirectional information-representative signal flow paths, and said cell interconnect means include means for driving information-representative signals along the flow path defined by said bus means.

Claim 4

Digital data processing apparatus as claimed in claim 1, characterised in that each stage of said shift register means includes means for storing a digital information-representative signal word of (n) digital bits, where (n) is a positive integer, and said cell interconnect means include timing control means responsive to at least one set of applied digital clock cycle signals for sequentially driving information-­representative digital words through successive stages of said shift register means at a rate responsive to the rate of said at least one set of digital clock cycles.

Claim 5

Data processing apparatus as claimed in claim 3, characterised in that said shift register means includes means for storing a given digital word in a given stage of said shift register means, and transferring a given digital word to a succeeding stage of said shift register means after an applied digital clock cycle, and each cell interconnect means has associated therewith a subset of (s) stages of said shift register means, where (s) is a positive integer, so that a given digital word is resident in a stage associated with each cell interconnect means for (s) applied digital clock cycles.

Claim 6

Data processing apparatus as claimed in claim 4 characterised in that said shift register means includes means for sequentially transferring digital signal packets comprising (w) corresponding digital words, where (w) is a positive integer, so that a digital word corresponding to a given digital signal packet is resident in at least one stage associated with a given cell interconnect means for (s) (w) applied digital clock cycles.

Claim 7

Data processing apparatus as claimed in claim 5, wherein said shift register means includes means for simultaneously transferring to successive shift register stages (p) digital signal packets, where (p) is a positive integer given by (p) = (c)(s)/(w) where (c) is the number of said cell interconnect means, (s) is the number of the said shift register stages associated with each said cell interconnect means and (w) is the number of digital words in each digital signal packet.

Claim 8

Data processing apparatus as claimed in claim 6, characterised in that at least one of said processing cells include means for generating and transmitting to an associated cell interconnect means a cell interconnect control signal representative of a request to store an information-representative signal in an associated stage of said shift register means.

Claim 9

Data processing apparatus as claimed in claim 6, characterised in that at least one of said processing cells includes means for generating and transmitting to an associated cell interconnect means a cell interconnect control signal representative of a request for access to an information-representative signal stored in an associated stage of said shift register means.

Claim 10

Data processing apparatus as claimed in claim 8, characterised in that said associated cell interconnect means includes means, responsive to said cell interconnect control signal, for extracting said information-representative signal stored in said associated stage of said shift register means and for transferring said extracted information-representative signal to said associated cell.

Claim 11

Data processing apparatus as claimed in claim 8, characterised in that said associated cell interconnect means includes means, responsive to said cell interconnect control signal, for replicating said information-representative signal stored in said associated stage of said shift register means and for transferring said replicated information-representative signal to said cell.

Claim 12

Data processing apparatus as claimed in claim 6, characterised in that at least one of said processing cells includes means for generating and transmitting to an associated cell interconnect means, a cell interconnect control signal representative of a request to transfer unchanged an information-­representative signal stored in a first associated stage of said shift register means to a second, succeeding associated stage of said shift register means.

Claim 13

Data processing apparatus as claimed in claim 11, wherein said associated cell interconnect means includes means, responsive to said cell interconnect control signal, for enabling transfer to said second, succeeding associated stage of said shift register means said information-representative signal stored in said first associated stage of said shift register means.

Claim 14

Data processing apparatus as claimed in claim 6, characterised in that at least one of said processing cells include means for generating and transmitting to an associated cell interconnect means a cell interconnect control signal representative of a request to identify a given digital word stored in an associated stage of said shift register means as the first word of a data packet.

Claim 15

Data processing apparatus as claimed in claim 13, characterised in that said associated cell interconnect means includes means, responsive to said cell interconnect control signal, for setting a portion of said given digital word to a selected value identifying said given digital word as the first word of said data packet.

Claim 16

Digital data processing apparatus as claimed in claim 1, characterised in that said cell interconnect means comprises a subset of serially connected stages of said shift register means.

Claim 17

Data processing apparatus as claimed in claim 6, characterised in that each said digital signal packet includes at least one digital word representative of a memory address, at least one digital word representative of a command, and at least one digital word representative of data.

Claim 18

Data processing apparatus as claimed in claim 6, wherein at least one of said processing cells includes means for generating and transmitting to an associated cell interconnect a plurality of cell interconnect control signals representative of a request to execute any of extracting, passing, and copying a given digital signal packet stored in said shift register means, and at least one cell interconnect means associated with said at least one processing cell includes means, responsive to said cell interconnect control signals, for assembling said digital signal packets.

Claim 19

Data processing apparatus as claimed in claim 11 characterised in that at least one of said processing cells includes means for addressing a directory lookup table and for retrieving therefrom a directory lookup value, and at least one cell interconnect means associated with said at least one processing cell includes means, responsive to said directory lookup value, for extracting a given digital signal packet stored in said shift register means.

Claim 20

Digital data processing apparatus comprising bus means for transferring information-­representative digital signals, said bus means including shift register means having a set of digital storage and transfer stages connected in series, for sequentially storing and transferring said information-representative digital signals, and a plurality of processing cells, connected to said bus means, at least one of said cells including any of (i) a central processing unit, (ii) an associated memory element for storing information-representative digital signals, coupled with said central processing unit for information transfer therebetween, and (iii) associated cell interconnect means, connected in circuit with said shift register means, and with an associated central processing unit, for transferring information-representative signals onto said shift register means, said cell interconnect means include timing control means, responsive to at least one set of applied digital clock cycle signals, for sequentially driving information-representative digital words through successive stages of said shift register means at a rate responsive to the rate of said at least one set of digital clock cycles, wherein as the number (s) of stages of said shift register means increases, the flux of said digital words through said stages of said shift register means remains constant.

Claim 21

Digital data processing apparatus comprising bus means for transferring information-­representative digital signals, said bus means including shift register means having a set of digital storage and transfer stages connected in series, for sequentially storing and transferring said information-representative digital signals, and a plurality of processing cells, connected to said bus means, at least one of said cells including any of (i) a central processing unit, (ii) an associated memory element for storing information-representative digital signals, coupled with said central processing unit for information transfer therebetween, and (iii) associated cell interconnect means, connected in circuit with said shift register means, and with an associated central processing unit, for transferring information-representative signals onto said shift register means, said cell interconnect means include timing control means, responsive to at least one set of applied digital clock cycle signals, for sequentially driving information-representative digital words through successive stages of said shift register means at a rate responsive to the rate of said at least one set of digital clock cycles, wherein as the number (s) of stages of said shift register means increases, the flux of said digital words through said stages of said shift register means remains constant.

Claim 22

Data processing apparatus as claimed in claim 19, characterised in that clock cycle skew associated with said at least one set of digital clock cycles remains substantially constant with reference to each of said (s) stages of said shift register means as the number (s) increases.