Patent US4145426A successfully refreshed from Google Patents.
Patent EP0321847A2 successfully refreshed from Google Patents.
EP0321847A2
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Semiconductor memory capable of improving data rewrite speed
Assignee: Toshiba Corp
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Filing: 1988-12-14
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Granted: —
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Expires: 2008-12-14
Abstract
Abstract A semiconductor memory device is disclosed which comprises, as shown in Fig. 1, a pair of column lines (BL₁, BL₁ ), memory cells (MC₁, MC₂) connected to the corresponding column lines, sense amplifier (10) connected to the column lines, row lines (WL₀, WL₁) for selecting the memory cells in accordance with a row address signal, and first and second transistors (Q₁₀, Q₁₁) having their current paths connected between the column lines and a fixed potential supply terminal (14) supplied with a positive power source potential or a ground potential, wherein the gates of the first and second transistors (Q₁₀, Q₁₁) are connected to the first and second row lines (WL₁₀, WL₁₁) for data rewrite operation which can be selected independently of the row line.
Inventors
- 👤 Koichi C/O Patent Division Magome
- 👤 Masakazu C/O Patent Division Kiryu
- 👤 Shigeo C/O Patent Division Ohshima
- 👤 Haruki C/O Patent Division Toda
- 👤 Hiroshi C/O Patent Division Sahara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 02:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/20; G11C11/401; G11C11/4063; G11C11/407; G11C11/4072; G11C11/409
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
74 words
A semiconductor memory device comprising a pair of column lines (BL₁, BL₁ ), memory cells (MC₁, MC₂) connected to the associated column lines, respectively a sense amplifier (10) connected to the column lines, and row lines (WL₀, WL₁) for selecting the memory cells in accordance with a corresponding address signal, characterized in that means is provided for writing all the same data "1" or "0" at a time into the memory cells (MC₁, MC₂).
Claim 2
Dependent Claim
74 words
A semiconductor memory device comprising a pair of column lines (BL₁, BL₁ ), memory cells (MC₁, MC₂) connected to the associated column lines, respectively a sense amplifier (10) connected to the column lines, and row lines (WL₀, WL₁) for selecting the memory cells in accordance with a corresponding address signal, characterized in that means is provided for writing all the same data "1" or "0" at a time into the memory cells (MC₁, MC₂).
Claim 3
Dependent Claim
84 words
The semiconductor memory device according to claim 1, characterized in that said means includes first and second transistors (Q₁₀, Q₁₁) having their current paths connected between said pair of column lines (BL₁, BL₁ ) and a fixed potential supply terminal (14) supplied with a positive power supply potential or a ground potential, and said first and second transistors (Q₁₀, Q₁₁) are connected at their gates to first and second data rewrite row lines (WL₁₀, WL₁₁) which can be selected independently of said row lines.
Claim 4
Dependent Claim
60 words
The semiconductor memory device according to claim 1 or 2, characterized in that said means includes switching transistors (Q₇, Q₈) and said pair of column lines (BL₁, BL₁ ) are connected to corresponding write data supply terminals (IN, IN ) via said switching transistors which are turned ON at a data write time and turned OFF at the other time.
Claim 5
Dependent Claim
31 words
The semiconductor memory device according to claim 1, 2 or 3, characterized in that said memory cells (MC₁, MC₂) each comprise a transistor (Q₁ or Q₂) and capacitor (C₁ or C₂).
Claim 6
Dependent Claim
28 words
The semiconductor memory device according to claim 3, characterized in that said write data supply terminals (IN, IN ) are grounded or connected to a positive source terminal.
Claim 7
Dependent Claim
57 words
The semiconductor memory device according to claim 3, characterized in that one of said write data supply terminals (IN, IN ) is connected to a corresponding switching transistor (Q₇, Q₈) via an inverter (A₁) which is supplied with write-in data and the other write data supply terminals (IN, IN ) is placed in an electrically floated state.
Claim 8
Dependent Claim
27 words
The semiconductor memory device according to claim 3, characterized in that a common signal line (F/WG) is connected to the gates of said switching transistors (Q₇, Q₈).
Claim 9
Dependent Claim
72 words
The semiconductor memory device according to claim 7, characterized in that when a potential on said common line (F/WG) becomes a predetermined level subsequent to the selection of said column and row lines and a potential on said column line (BL) becomes a predetermined level, said sense amplifier sets said potential on said column line to a predetermined level to allow predetermined data "0" or "1" to be written into associated cells.
Claim 10
Dependent Claim
44 words
The semiconductor memory device according to claim 3, characterized in that a buffer (A₁) writes predetermined data "0" or "1" into all cells on said row lines (WL₀) at a time upon receipt of an input signal (F/WD IN ) of a predetermined level.
References Cited (Backward Citations)
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