Data demodulator baud clock phase locking

Claim 3

A method as claimed in Claim 1, characterised in that the phase of the baud rate clock is advanced or retarded only in respect of successive pairs of early or late pulses, as the case may be.

Claim 4

A method as claimed in Claim 1 or Claim 2, characterised in that a number of early or late detections are averaged over a period before an increment of phase adjustment of the baud rate clock phase is effected.

Claim 5

An arrangement for phase-locking a locally generated baud rate clock to the baud rate of a received shift keyed signal which is phase-modulated to represent digital data, comprising:- - input means for receiving a phase-modulated shift keyed signal of a given carrier frequency; - reference signal generator means for producing two quadrature phase versions of a locally generated carrier signal of said given frequency; - multiplier means connected to receive said shift keyed signal and said two locally generated carrier signal versions and operable to multiply separately the shift keyed signal with each said version to produce two bi-level channel signals; - first measuring means connected to receive said two channel signals and operable in respect of each to produce for each period thereof occurring in each successive half cycle of one of the channel signals a first sign signal representing which is the predominant level of this channel signal in the period; - second measuring means connected to receive said two channel signals and operable in respect of each to produce for each period thereof occurring in each succesive half cycle of the other of the two channel signals a second sign signal representing which is the predominant level of ths other channel signal in the period; - pulse means for producing a narrow pulse in respect of each of the four sign signals thus produced; - combining means for combining all the narrow pulses into a single continuous pulse sequence; - detector means for detecting in each period of the baud rate clock which narrow pulses in the sequence are early and which are late relative to an edge of the baud rate clock pulses; and - means for advancing or retarding the phase of the baud rate clock in accordance with this detection to adjust the baud rate clock phase into a desired phase relationship with the baud rate transitions in the received shift keyed signal.

Claim 6

An arrangement for phase-locking a locally generated baud rate clock to the baud rate of a received shift keyed signal which is phase-modulated to represent digital data, comprising:- - input means for receiving a phase-modulated shift keyed signal of a given carrier frequency; - reference signal generator means for producing two quadrature phase versions of a locally generated carrier signal of said given frequency; - multiplier means connected to receive said shift keyed signal and said two locally generated carrier signal versions and operable to multiply separately the shift keyed signal with each said version to produce two bi-level channel signals; - first measuring means connected to receive said two channel signals and operable in respect of each to produce for each period thereof occurring in each successive half cycle of one of the channel signals a first sign signal representing which is the predominant level of this channel signal in the period; - second measuring means connected to receive said two channel signals and operable in respect of each to produce for each period thereof occurring in each succesive half cycle of the other of the two channel signals a second sign signal representing which is the predominant level of ths other channel signal in the period; - pulse means for producing a narrow pulse in respect of each of the four sign signals thus produced; - combining means for combining all the narrow pulses into a single continuous pulse sequence; - detector means for detecting in each period of the baud rate clock which narrow pulses in the sequence are early and which are late relative to an edge of the baud rate clock pulses; and - means for advancing or retarding the phase of the baud rate clock in accordance with this detection to adjust the baud rate clock phase into a desired phase relationship with the baud rate transitions in the received shift keyed signal.

Claim 7

An arrangement as claimed in Claim 4, characterised in that said first and second measuring means comprise two exclusive-OR gates connected to receive in common at respective first inputs a square wave version of the received signal and at respective second inputs respective quadrature phase versions of square wave form of a locally generated carrier signal, first and second pairs of up/down counters, the up/down operation mode of one counter of each pair being controlled by the output signal from one of said two exclusive-OR gates and the up/down operation mode of the other counter of each pair being controlled by the output signal from the other of said two exclusive-OR gates, each of said counters being connected to receive counting pulses from a count clock pulse source and each counter of one pair being reset by a reset signal on the occurrence of each edge of one of the two locally generated signals and each counter of the other pair being reset by a reset signal on the occurrence of each edge of the other of the two locally generated carrier signals, the count present in each counter immediately before being reset each time representing the difference in the durations of the two levels of the relevant channel signal and the direction of the count respectively the sign of the difference, said sign signals being derived from said difference representation.

Claim 8

An arrangement as claimed in Claim 5, characterised in that each of said counters is a binary counter and the counters have associated with them respective latching means into which their counts are latched.

Claim 9

An arrangement as claimed in Claim 6, characterised in that said means for producing the narrow pulses from the sign signals are monostable circuits which are connected to receive a respective one of the sign signals from the counters.

Claim 10

An arrangement as claimed in any one of Claims 4 to 7, characterised in that transversal filters are provided to which early and late pulses produced by the detector means are applied, respectively, these filters operating to average these pulses over a period before producing an output signal to cause phase adjustment of the baud rate clock.

Claim 11

An arrangment as claimed in Claim 8, characterised in that said baud rate clock is comprised by a counter which is fed with drive pulses from an associated drive circuit which is connected to a drive pulse clock source and also connected to receive the output signals from said filters, which drive circuit is responsive according to which filter on output signal is received from to add or delete drive pulses as applied by it from the drive pulse clock source to the counter.

Claim 12

A coherent data demodulator embodying a phase-locking arrangement as claimed in any one of Claims 4 to 9.