Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
253 words
1)Self adjusting phase lock circuit, of the type comprising first means for comparing the frequency and/or phase of a reference signal (VCO) with a periodical input signal (RD) having variable frequency and for generating a voltage (VC) related to the frequency/phase error of the two reference and input signals and further comprising a voltage controlled oscillator receiving said voltage VC at a control input, an adjusting voltage (VRANGE) at an adjusting input and outputing said reference signal VCO as a function of voltages VC and VRANGE, said phase lock circuit being characterized by comprising: - second means for decoupling said voltage VC from said control input and for applying to said control input a predetermined reference voltage, - third means for comparing the frequency of said reference signal VCO with a nominal working frequency (FR) and for generating a voltage related to the error between said frequency FR and the frequency of said VCO reference signal, - fourth means, operational on the voltage generated by said third means, for generating said adjusting voltage VRANGE, - fifth means for sampling and holding said adjusting voltage VRANGE, - sixth high input impedance means for applying said voltage VRANGE sampled and hold by said fifth means to said adjusting input, - seventh means for sinchronously controlling said second and fifth means to respectively decouple and sample, - said third, fourth, fifth, sixt means and said oscillator forming a feedback control loop of the frequency of said signal VCO wherein said voltage VRANGE is the feedback signal.
Claim 2
Dependent Claim
253 words
1)Self adjusting phase lock circuit, of the type comprising first means for comparing the frequency and/or phase of a reference signal (VCO) with a periodical input signal (RD) having variable frequency and for generating a voltage (VC) related to the frequency/phase error of the two reference and input signals and further comprising a voltage controlled oscillator receiving said voltage VC at a control input, an adjusting voltage (VRANGE) at an adjusting input and outputing said reference signal VCO as a function of voltages VC and VRANGE, said phase lock circuit being characterized by comprising: - second means for decoupling said voltage VC from said control input and for applying to said control input a predetermined reference voltage, - third means for comparing the frequency of said reference signal VCO with a nominal working frequency (FR) and for generating a voltage related to the error between said frequency FR and the frequency of said VCO reference signal, - fourth means, operational on the voltage generated by said third means, for generating said adjusting voltage VRANGE, - fifth means for sampling and holding said adjusting voltage VRANGE, - sixth high input impedance means for applying said voltage VRANGE sampled and hold by said fifth means to said adjusting input, - seventh means for sinchronously controlling said second and fifth means to respectively decouple and sample, - said third, fourth, fifth, sixt means and said oscillator forming a feedback control loop of the frequency of said signal VCO wherein said voltage VRANGE is the feedback signal.
Claim 3
Dependent Claim
43 words
2) Phase lock circuit as claimed in claim 1, wherein said third means comprises said first means and further eight means for substituting said nominal working frequency FR to said periodical input signal RD having variable frequency, as input to said first means.
Claim 4
Dependent Claim
214 words
3) Phase lock circuit as claimed in claim 1, wherein said first means compreses A) a phase comparator for comparing the phase of said reference signal VCO with the phase of said periodical input signal RD and for generating at least a first phase error signal (PUP), a frequency comparator for comparing the frequency of said nominal working frequency FR with the frequency of said reference signal (VCO) and for generating a frequency error signal (FPUMP), and B) an integrating network of said first phase error and said frequency error for generating an error voltage (VC) related to said phase and frequency errors, and wherein - said second means comprises a first analogic switch and a voltage divider connected to the output of said first switch, - said third means comprises said frequency comparator, said integrating network and a second analogic switch for decoupling said first phase error signal from input to said integrating network, - said fourth means comprises a first operational amplifier performing a subtractive with gain operation of the voltage generated by said third means from a reference voltage, and - said fifth means comprises a third analogic switch connected to the output of said first operational amplifier and a capacitor connected between the output of said third switch and ground.