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EP0320607A2
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Multiprocessor system featuring global data duplication
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1988-10-29
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Granted: —
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Expires: 2008-10-29
Abstract
Abstract Multiprocessor computing system wherein a plurality of processors are connected each other through a system bus, each processor comprising a processing unit, a local memory and an interface unit, and wherein the processing unit of any processor has access to both its own local memory and the local memory of any other processor (through the interface unit and the system bus) for concurrently writing into all the local memories an information identified by a destination code as a global data to be concurrently written in all local memories.
Inventors
- 👤 Ferruccio Zulian
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 22:26
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/161
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
170 words
1) Multiprocessor computing system wherein a plurality of processors, are connected each other through a system bus, each processor comprising a processing unit, a local memory and an interface unit, the processing unit of one processor having access to the local memory of the same processor without need of getting access to the system bus, a processing unit of any one processor having access to the local memory of another processor through said system bus and the interface unit of both processors, an information to be stored in any one of said local memories being referenced by an address code comprising a destination code identifying an information as be stored in a prestablished one of said local memories, characterized in that said destination code has a binary configuration which identifies an information as a global data, each processor having: means responsive to said global data binary configuration to concurrently perform a write operation of an information identified as a global data into the local memory of all of said processors.
Claim 2
Dependent Claim
170 words
1) Multiprocessor computing system wherein a plurality of processors, are connected each other through a system bus, each processor comprising a processing unit, a local memory and an interface unit, the processing unit of one processor having access to the local memory of the same processor without need of getting access to the system bus, a processing unit of any one processor having access to the local memory of another processor through said system bus and the interface unit of both processors, an information to be stored in any one of said local memories being referenced by an address code comprising a destination code identifying an information as be stored in a prestablished one of said local memories, characterized in that said destination code has a binary configuration which identifies an information as a global data, each processor having: means responsive to said global data binary configuration to concurrently perform a write operation of an information identified as a global data into the local memory of all of said processors.
Claim 3
Dependent Claim
50 words
2) Multiprocessor system as claimed in claim 1 comprising means responsive to said global data binary configuration on said system bus for acknowledging (90,89,85,87) execution of a write operation once all said local memories, referenced through said global data binary configuration on said system bus have performed said write operation.
Claim 4
Dependent Claim
69 words
3) Multirocessor system as claimed in claim 1 wherein said means comprise a decoder (37, 38) responsive to said global data binary configuration to provide a selection signal (S1, S2) which selects both the local memory of the related processor, for a write operation and the interface unit of the related processor, for requesting a bus access and the broadcasting of a write operation request to all other processors.
Claim 5
Dependent Claim
54 words
4) Multiprocessor system as claimed in claim 1 wherein said means comprise a decoder (70) responsive to said global data binary configuration when received from said system bus, to provide an access request signal (MYSP) to the related processor, for directing the local memory reference present on the system bus to the related processor.
Claim 6
Dependent Claim
47 words
5) Multiprocessor system as claimed in claim 4 wherein said decoder (70) has a control input (BEN) preventing the recognition of said global data binary configuration, present on said system bus, when said global data binary configuration is issued on said system bus by the related processor.
Claim 7
Dependent Claim
29 words
6) Multiprocessor as claimed in claim 5 comprising means (82) for converting said global data binary configuration in a destination code referencing the local memory of the related processor.
References Cited (Backward Citations)
No citation records indexed.
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