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EP0320405A2
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Semiconductor static random access memory device
Assignee: Fujitsu Ltd
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Filing: 1988-12-09
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Granted: —
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Expires: 2008-12-09
Abstract
Abstract Static random access memory device composed of resistance loaded flip flop circuits. Adjacent memory cells are arranged to form memory cell pairs composed by a unit cell 1 and a unit cell 2. Load resistors (R11, R12) for the unit cell 1 and those (R21, R22) for the unit cell (2) are formed on different insulation layers (8, 9) and stacked on each other. By taking such a configuration, the pattern of the load resistors is extended over an adjacent memory cell. So, the length and resistance of the resistors are increased by two compared to those of the prior art. The length of the load resistors can be cut down for compensating the increase of the resistance. This enables fabrication of devices 1/2 size of the prior art, and the packing density of the devices is increased by four.
Inventors
- 👤 Taiji Ema
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 01:08
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/15; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
142 words
A semiconductor static random access memory device (SRAM) formed on a semiconductor substrate (7) and plurality of insulation layers formed over said semiconductor substrate, said SRAM comprising a plurality of unit cell pairs, each of said unit cell pairs being composed of a first unit cell (1) and a second unit cell (2), said first unit cell and second unit cell respectively comprising a flip flop circuit which is formed by a pair of resistor loaded inverters, each of said resistor loaded inverters comprising an inverter transistor (Q11, Q12, Q21, Q22) composed of a field effect transistor (FET) formed in said substrate and a load resistor (R11, R12, R21, R22,) wherein the load resistors (R11, R12) for said first unit cells (1) and the load resistors (R21, R22) for said second unit cells (2) are formed on different insulation layers (8, 9).
Claim 2
Dependent Claim
142 words
A semiconductor static random access memory device (SRAM) formed on a semiconductor substrate (7) and plurality of insulation layers formed over said semiconductor substrate, said SRAM comprising a plurality of unit cell pairs, each of said unit cell pairs being composed of a first unit cell (1) and a second unit cell (2), said first unit cell and second unit cell respectively comprising a flip flop circuit which is formed by a pair of resistor loaded inverters, each of said resistor loaded inverters comprising an inverter transistor (Q11, Q12, Q21, Q22) composed of a field effect transistor (FET) formed in said substrate and a load resistor (R11, R12, R21, R22,) wherein the load resistors (R11, R12) for said first unit cells (1) and the load resistors (R21, R22) for said second unit cells (2) are formed on different insulation layers (8, 9).
Claim 3
Dependent Claim
138 words
A semiconductor static random access memory device as set forth in claim 1, in which : each of said first unit cells (1) further comprises a first voltage source line (Vcc1) for supplying a source voltage to said first unit cell ; and each of said second unit cells (2) further comprises a second voltage source line (Vcc2) for supplying a source voltage to said second unit cell, wherein : said load resistors (R11, R12) of said first unit cell (1) and said first voltage source line (Vcc1) are formed on a first insulation layer (8) formed over said substrate (7) ; and said load resistors (R21, R22) of said second unit cell (2) and said second voltage source line (Vcc2) are formed on a second insulation layer (9) which is formed over said first insulation layer (8).
Claim 4
Dependent Claim
172 words
A semiconductor static random access memory device as set forth in claim 1, in which : each of said first unit cells (1) further comprises a first voltage source line (Ucc1) for supplying the source voltage to said first unit cell, and each of said second unit cells (2) further comprises a second voltage source line (Vcc2) for supplying the source voltage to said second unit cell, wherein : said first voltage source line (Vcc1) is formed on a first insulation layer (8), which is formed over said substrate (7) ; said load resistors (R11, R12) of said first unit cell (1) are formed on a third insulation layer (8′) which is formed over said first insulation layer (8) ; said second voltage source line (Vcc2) is formed on a second insulation layer (9), which is formed over said third insulation layer (8′) ; and said load resistors (R21, R22) of said second unit cell (2) are formed on a fourth insulation layer (9′) which is formed over said insulation layer (9).
Claim 5
Dependent Claim
107 words
A semiconductor static random access memory device as set forth in claim 2, in which each of said unit cells (1, 2,) further comprises transfer transistors (T11, T12, T21, T22) each connected with a respective inverter transistor and composed of a FET formed in said substrate (7) and positioning in peripheral portion of said inverter transistors (Q11, Q12, Q21, Q22) for sending out an information whether said inverter is in high state or low state to an outer circuit, wherein : load resistors (R21, R22) formed on said second insulation layer (9) are longer than the load resistors (R11, R12) formed on said first insulation layer (8).
Claim 6
Dependent Claim
34 words
A semiconductor static random access memory device as set forth in claim 1, 2, 3 or 4, wherein said substrate (7) is a silicon substrate, and said insulation layers are silicon dioxide (SiO₂) layers.
Claim 7
Dependent Claim
36 words
A semiconductor static random access memory device as set forth in claim 1, 2, 3 or 4, wherein said load resistors (R11, R12, R21, R22) and said voltage source lines (Vcc1, Vcc2) are made from polysilicon.
Claim 8
Dependent Claim
32 words
A semiconductor static random access memory device as set forth in claim 3 or 4, wherein the thickness of said load resistors is less than the thickness of said voltage source lines.
References Cited (Backward Citations)
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