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EP0319432A2
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Semiconductor memory device with serial access memory
Assignee: Fujitsu VLSI Ltd
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Filing: 1988-12-02
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Granted: —
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Expires: 2008-12-02
Abstract
Abstract A semiconductor memory device includes : a first memory cell array (40) having a plurality of memory cells (M) arrayed in a row direction and a column direction; a second memory cell array (44) having at least serial access memory cells (MC₁ - MC n ) corresponding to a single row of the first memory cell array; a first data bus (DB₀ , DB ₀); and a second data bus (DB E , DB E ); a third data bus (DB X , DB X ); and a bus switching control circuit (45, 46, 57, 60) for controlling a connection of each of the serial accesss memory cells to one of the first, second and third data buses and selecting one of the buses to connect the selected data bus to the external of the device. The bus switching control circuit outputs each of bit data in the serial access memory cells serially and alternately to the first and second data buses and, where a plurality of transfer data blocks are serially read out from the second memory cell array, outputs a bit data in the serial access memory cell corresponding to the head or last address in each of the transfer data blocks to the third data bus. As a result, it is possible to prevent interruption from being generated between the transfer data blocks in the serial data transfer operation and thus to increase the data transfer speed.
Inventors
- 👤 Tsutomu Sugiyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 17:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/00; G11C7/10; G11C7/1048; G11C7/1075; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
264 words
A semiconductor memory device comprising: a first memory cell array (40) having a plurality of random access memory cells (M) arrayed in a row direction and a column direction; a second memory cell array (44; 44a, 44b) operatively connected to said first memory cell array and having at least serial access memory cells (MC₁ - MC n ) corresponding to a single row of said first memory cell array; a first data bus (DB₀ , DB₀ ) allocated to serial access memory cells corresponding to odd number addresses; a second data bus (DB E , DB E ) allocated to serial access memory cells corresponding to even number addresses; a third data bus (DB X , DB X ) allocated to at least one specific serial access memory cell; and a bus switching control circuit (45, 45′, 45a, 45b 46, 57, 57a, 57b, 58, 60, 60′) for controlling a connection of each of said serial access memory cells to one of said first, second and third data buses and selecting one of the data buses to connect the selected data bus to the external of said device, said bus switching control circuit outputting each of bit data in said serial access memory cells serially and alternately to said first and second data buses and, where a plurality of transfer data blocks are serially read out from said second memory cell array, outputting a bit data in said at least one specific serial access memory cell corresponding to the head or last address in each of said transfer data blocks to said third data bus.
Claim 2
Dependent Claim
264 words
A semiconductor memory device comprising: a first memory cell array (40) having a plurality of random access memory cells (M) arrayed in a row direction and a column direction; a second memory cell array (44; 44a, 44b) operatively connected to said first memory cell array and having at least serial access memory cells (MC₁ - MC n ) corresponding to a single row of said first memory cell array; a first data bus (DB₀ , DB₀ ) allocated to serial access memory cells corresponding to odd number addresses; a second data bus (DB E , DB E ) allocated to serial access memory cells corresponding to even number addresses; a third data bus (DB X , DB X ) allocated to at least one specific serial access memory cell; and a bus switching control circuit (45, 45′, 45a, 45b 46, 57, 57a, 57b, 58, 60, 60′) for controlling a connection of each of said serial access memory cells to one of said first, second and third data buses and selecting one of the data buses to connect the selected data bus to the external of said device, said bus switching control circuit outputting each of bit data in said serial access memory cells serially and alternately to said first and second data buses and, where a plurality of transfer data blocks are serially read out from said second memory cell array, outputting a bit data in said at least one specific serial access memory cell corresponding to the head or last address in each of said transfer data blocks to said third data bus.
Claim 3
Dependent Claim
72 words
A device as set forth in claim 1, wherein said bus switching control circuit comprises a pointer (57) which determines said head address in said transfer data block and said last address therein, a serial access memory cell corresponding to said head address being connected to one of said first and second data buses and a serial access memory cell corresponding to said last address being connected to said third data bus.
Claim 4
Dependent Claim
29 words
A device as set forth in claim 2, wherein said last address in said transfer data block is fixed to the last address in said second memory cell array.
Claim 5
Dependent Claim
113 words
A device as set forth in claim 3, wherein said bus switching control circuit further comprises a control circuit (60) which generates a first control clock (S₀) for said first data bus and a second control clock (S E ) for said second data bus alternately in response to a serial access strobe signal (SAS) and generates a third control clock (S X ) for said third data bus in response to a signal (S n ) indicating said last address fed from said pointer, and a multiplexer (46) which responds to one of said first, second and third control clocks and connects the corresponding data bus to the external of said device.
Claim 6
Dependent Claim
66 words
A device as set forth in claim 4, wherein said bus switching control circuit further comprises at least two reset circuits (RC) which short-circuit said first and second data buses to bring said data buses to reset states when a bit data is output from the serial access memory cell corresponding to said last address via said third data bus to the external of said device.
Claim 7
Dependent Claim
85 words
A device as set forth in claim 5 wherein said bus switching control circuit further comprises a bus selecting circuit (45) connected between said second memory cell array and said data buses and having selecting circuits (BS₁ - BS n ) provided for each of said serial access memory cells, each of said selecting circuits connecting the corresponding serial access memory cell to one of said data buses in response to a corresponding bus select signal (S₁ - S n ) fed from said pointer.
Claim 8
Dependent Claim
75 words
A device as set forth in claim 1, wherein said bus switching control circuit comprises a pointer (57) determining said head address in said transfer data block and a counter (58) determining said last address therein, a serial access memory cell corresponding to said head address being connected to one of said first and second data buses and a serial access memory cell corresponding to said last address being connected to said third data bus.
Claim 9
Dependent Claim
36 words
A device as set forth in claim 7, wherein said last address in said transfer data block is selectable in accordance with a timing of application of an external control signal ( TR / OE ).
Claim 10
Dependent Claim
104 words
A device as set forth in claim 8, wherein said bus switching control circuit further comprises a control circuit (60′) which generates a first control clock (S₀) for said first data bus and a second control clock (S E ) for said second data bus alternately in response to a serial access strobe signal (SAS) and generates a third control clock (S X ) for said third data bus in response to said external control signal, and a multiplexer (46) which responds to one of said first, second and third control clocks and connects the corresponding data bus to the external of said device.
Claim 11
Dependent Claim
66 words
A device as set forth in claim 9, wherein said bus switching control circuit further comprises at least two reset circuits (RC) which short-circuit said first and second data buses to bring said data buses to reset states when a bit data is output from the serial access memory cell corresponding to said last address via said third data bus to the external of said device.
Claim 12
Dependent Claim
100 words
A device as set forth in claim 10, wherein said bus switching control circuit further comprises a bus selecting circuit (45′) connected between said second memory cell array and said data buses and having selecting circuits (BS₁′ - BS n ′) provided for each of said serial access memory cells, each of said selecting circuits connecting the corresponding serial access memory cell to one of said data buses in response to a corresponding bus select signal (S₁ - S n ) fed from said pointer or a corresponding bus change signal (S₁′ - S n ′) fed from said counter.
Claim 13
Dependent Claim
72 words
A device as set forth in claim 1, wherein said bus switching control circuit comprises a pointer (57) which determines said head address in said transfer data block and said last address therein, a serial access memory cell corresponding to said last address being connected to one of said first and second data buses and a serial access memory cell corresponding to said head address being connected to said third data bus.
Claim 14
Dependent Claim
29 words
A device as set forth in claim 12, wherein said head address in said transfer data block is fixed to the head address in said second memory cell array.
Claim 15
Dependent Claim
111 words
A device as set forth in claim 13, wherein said bus switching control circuit further comprises a control circuit (60) which generates a first control clock (S₀) for said first data bus and a second control clock (S E ) for said second data bus alternately in response to a serial access strobe signal (SAS) and generates a third control clock (S X ) for said third data bus in response to a signal (S₁) indicating said head address fed from said pointer, and a multiplexer (46) which responds to one of said first, second and third control clocks and connects the corresponding data bus to the external of said device.
Claim 16
Dependent Claim
77 words
A device as set forth in claim 6, wherein said second memory cell array, said pointer and said bus selecting circuit are constituted in a duplicated form and said bus switching control circuit further comprises a second multiplexer (59) connected between said first memory cell array and said second memory cell arrays in said duplicated form, said second multiplexer connecting one of said second memory cell arrays in said duplicated form to said first memory cell array.
References Cited (Backward Citations)
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