Patent EP0317963A2 successfully refreshed from Google Patents.
EP0317963A2
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EP
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Semiconductor memory device having dRAM cells
Assignee: Toshiba Corp
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Filing: 1988-11-22
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Granted: —
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Expires: 2008-11-22
Abstract
Abstract Data of "0" and "1" are input to input pad (10) which is provided for each dRAM chip. The data is input to two data input buffers (14a, 14b) via protection circuit 12. Each of data input buffers (14a, 14b) senses the level of input data, converts the sensed level to the MOS level and outputs the MOS level data. Data input buffers (14a, 14b) are respectively supplied with control signals (φa, φb) for determining the sense-timings thereof. The phases of control signals (φa, φb) are shifted from each other. Selection circuit (16) selects an output of one of data input buffers (14a, 14b) in synchronism with control signals (φa, φb) and supply the selected output to a corresponding one of write data line (18). Since two data input buffers are used, each data input buffer may operate to sense every other input data and each of control signals (φa, φb) is set to have a pulse occurring in every two cycles of the input data.
Inventors
- 👤 Takayuki C/O Patent Division Kobayashi
- 👤 Yukihito C/O Patent Division Oowaki
- 👤 Koji C/O Patent Division Sakui
- 👤 Yasuo C/O Patent Division Itoh
- 👤 Shigeyoshi C/O Patent Division Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 11:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/10; G11C7/1078; G11C7/1093; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/1087
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
70 words
A semiconductor memory device comprising: a data input pad; a plurality of data input buffers connected in parallel with said data input pad and for sequentially sensing input data periodically input; and selection means for receiving outputs from said plurality of data input buffers, sequentially selecting the outputs according to a cycle of the input data and supplying a selected output to a memory cell via a write data line.
Claim 2
Dependent Claim
70 words
A semiconductor memory device comprising: a data input pad; a plurality of data input buffers connected in parallel with said data input pad and for sequentially sensing input data periodically input; and selection means for receiving outputs from said plurality of data input buffers, sequentially selecting the outputs according to a cycle of the input data and supplying a selected output to a memory cell via a write data line.
Claim 3
Dependent Claim
93 words
A semiconductor memory device according to claim 1, characterized in that said plurality of data input buffers are respectively supplied with a plurality of control signals which are set in the same cycles as those of the input data and whose phases are shifted from one another, and said data input buffer includes means for sensing the input data of TTL (transistor-transistor-logic) level and converting the input data to data of MOS (metal-oxide-semiconductor) level and means for transferring the sensed MOS level data to said selection means in response to the control signal.
Claim 4
Dependent Claim
33 words
A semiconductor memory device according to claim 2, characterized in that said data input buffer further includes means for resetting the sensed data after a predetermined time in response to the control signal.
Claim 5
Dependent Claim
43 words
A semiconductor memory device according to claim 1, characterized in that said selection means sequentially selects one of outputs of said plurality of data input buffers and sequentially supplies the selected data to a corresponding one of a plurality of write data lines.
Claim 6
Dependent Claim
90 words
A semiconductor memory device according to claim 4, characterized in that said selection means includes first gate means connected to said plurality of write data lines to receive all the outputs of said plurality of data input buffers and to be sequentially turned on in each cycle of the control signal supplied to said data input buffer and second gate means for receiving each of outputs of said first gate means and selecting an output of that one of said data input buffers which is supplied with the control signal.
Claim 7
Dependent Claim
113 words
A semiconductor memory device comprising: memory cell groups of first and second planes; 2m I/O (input/output) lines, m I/O lines being provided for each of the first and second planes; bit lines connected to said I/O lines, each of the bit lines being connected to a number of dRAM cells; 2m write data lines respectively connected to said 2m I/O lines; a plurality of data input buffers connected to a data input pad to sequentially sense input data periodically input; and selection means for receiving outputs of said plurality of data input buffers, sequentially selecting the outputs and transferring the selected output to a corresponding one of a plurality of write data lines.
Claim 8
Dependent Claim
113 words
A semiconductor memory device comprising: memory cell groups of first and second planes; 2m I/O (input/output) lines, m I/O lines being provided for each of the first and second planes; bit lines connected to said I/O lines, each of the bit lines being connected to a number of dRAM cells; 2m write data lines respectively connected to said 2m I/O lines; a plurality of data input buffers connected to a data input pad to sequentially sense input data periodically input; and selection means for receiving outputs of said plurality of data input buffers, sequentially selecting the outputs and transferring the selected output to a corresponding one of a plurality of write data lines.
Claim 9
Dependent Claim
75 words
A semiconductor memory device according to claim 6, characterized in that said bit lines in each of the first and second planes include n groups of m bit lines, said m bit lines of each group are connected to said m I/O lines via a corresponding one of column selectors; and said column selectors connected to said m bit lines are sequentially activated to alternately select said memory call groups of first and second planes.
Claim 10
Dependent Claim
38 words
A semiconductor memory device according to claim 6, characterized in that said write data lines are connected to said I/O lines via gate stages which are sequentially turned on each time data is transferred from said selection means.
Claim 11
Dependent Claim
109 words
A semiconductor memory device according to claim 6, characterized in that said selection means includes 2m AND gate means provided correspondingly to said 2m number of write data lines to receive all the outputs of said plurality of data input buffers and to be sequentially turned on each time each of said data input buffers is operated; and gate means connected to receive outputs of said AND gate means and provided correspondingly to said plurality of data input buffers, and for selecting an output of that one of said data input buffers which is in operation and supplying the output to a corresponding one of said 2m data lines.
References Cited (Backward Citations)
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