Abstract Amplifier circuit, for example, a class AB output stage, comprising a series arrangement of a first transistor (T₁) and a second transistor (T₂) both arranged as diodes, a series arrangement of a third transistor (T₃) and a fourth transistor (T₄) and a series arrangement of a fifth transistor (T₅) and an impedance (R). The first main electrode of the first transistor (T₁) is coupled via the impedance (R) to the control electrode of the fourth transistor (T₄). The first main electrode of the second and the fifth transistor (T₂ , T₅) are coupled together and to the control electrode of the third transistor (T₃). The control electrodes of the first, second and fifth transistors (T₁, T₂ and T₅) are coupled together and to the second main electrodes of the first and the second transistor. A small quiescent current in the output transistors is possible in this circuit using relatively small input transistors (T₁, T₂) and relatively large output transistors (T₃, T₄).
An amplifier circuit comprising an input terminal, a series arrangement of a first transistor of a first conductivity type and a second transistor of a second conductivity type both arranged as diodes, and a series arrangement of a third transistor of the first conductivity type and a fourth transistor of the second conductivity type, each transistor having a first and a second main electrode and a control electrode, the control electrodes of the first and the second transistor being interconnected, the first main electrode of the first transistor being coupled to the control electrode of the fourth transistor, the first main electrode of the second transistor being coupled to the control electrode of the third transistor, and the intercoupled first main electrodes of the third and the fourth transistor being also coupled to an output terminal, characterized in that a series arrangement of an impedance and a fifth transistor of the second conductivity type is arranged parallel to the series arrangement of the first and the second transistor, the control electrode of the second transistor being coupled to the control electrode of the fifth transistor, the first main electrode of the first transistor being coupled via the impedance to the control electrode of the fourth transistor and the first main electrode of the second transistor being coupled to the first main electrode of the fifth transistor.
Claim 2
Dependent Claim
226 words
An amplifier circuit comprising an input terminal, a series arrangement of a first transistor of a first conductivity type and a second transistor of a second conductivity type both arranged as diodes, and a series arrangement of a third transistor of the first conductivity type and a fourth transistor of the second conductivity type, each transistor having a first and a second main electrode and a control electrode, the control electrodes of the first and the second transistor being interconnected, the first main electrode of the first transistor being coupled to the control electrode of the fourth transistor, the first main electrode of the second transistor being coupled to the control electrode of the third transistor, and the intercoupled first main electrodes of the third and the fourth transistor being also coupled to an output terminal, characterized in that a series arrangement of an impedance and a fifth transistor of the second conductivity type is arranged parallel to the series arrangement of the first and the second transistor, the control electrode of the second transistor being coupled to the control electrode of the fifth transistor, the first main electrode of the first transistor being coupled via the impedance to the control electrode of the fourth transistor and the first main electrode of the second transistor being coupled to the first main electrode of the fifth transistor.
Claim 3
Dependent Claim
63 words
An amplifier circuit as claimed in Claim 1, characterized in that the impedance is a resistor having a resistance R which is equal to (1/S₁ + 1/S₂) 1/m in which S₁ and S₂ are the slopes of the first and the second transistor, respectively, and m is the ratio of the gain factors of the fifth transistor with respect to the second transistor.