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EP0316087A2
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Method and apparatus for synchronising a plurality of processors
Assignee: Tandem Computers Inc
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Filing: 1988-10-24
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Granted: —
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Expires: 2008-10-24
Abstract
Abstract A method and apparatus for synchronizing a plurality of processors (6). Each processor runs off of its own independent clock (84), indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait (96) state. Each processor has a counter (102) which counts the number of processor events indicated since the last time the processors were synchronized. When an event requiring synchronization is detected by a sync logic circuit (110) associated with the processor, the sync logic circuit generates the wait signal (96) after the next processor event. A compare circuit (106) associated with each processor then tests the other event counters in the system and determines whether its associated processor is behind the others. If so, the sync logic circuit removes the wait signal until the next processor event. The processor is finally stopped when its event counter matches the event counter for the fastest processor. At that time, all processors are synchronized and may be restarted for servicing the event. If no synchronizing event occurs before an event counter reaches its maximum value, and overflow (126) of the event counter forces resynchronization. A cycle counter (100) is provided for counting the number of clock cycles since the last processor event. The cycle counter is set to overflow and force resynchronization at a point before maximum interrupt latency time is exceeded.
Inventors
- 👤 Robert W. Horst
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 23:26
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/183; G06F11/184; G06F11/1658; G06F11/1666; G06F11/1675; G06F11/1683; G06F11/1687; G06F11/1691; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F11/1679; G06F11/185; G06F11/20; G11; G11C; G11C29/00; G11C29/70; G11C29/74
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
82 words
An apparatus for synchronizing a plurality of processors comprising: event indicating means for indicating the occurrence of a prescribed event within an associated processor; event counting means, connected to the event indicating means, for counting the number of events indicated for each processor; and suspensions means, connected to the event counting means and to each processor, for suspending processing of a processor when the number of events counted for that processor is greater than the number of events counted for another processor.
Claim 2
Independent Claim
82 words
An apparatus for synchronizing a plurality of processors comprising: event indicating means for indicating the occurrence of a prescribed event within an associated processor; event counting means, connected to the event indicating means, for counting the number of events indicated for each processor; and suspensions means, connected to the event counting means and to each processor, for suspending processing of a processor when the number of events counted for that processor is greater than the number of events counted for another processor.
Claim 3
Dependent Claim
59 words
The apparatus according to claim 1 further comprising sync request means, connected to the suspension means, for receiving a synchronization request signal, wherein the suspension means suspends processing of a processor in response to the synchronization request signal when the number of events counted for that processor is not less than the number of events counted for another processor.
Claim 4
Dependent Claim
35 words
The apparatus according to claim 2 further comprising restart means, connected to the suspension means and to each processor, for restarting a suspended processor when the number of events counted for each processor is equal.
Claim 5
Dependent Claim
37 words
The apparatus according to claim 3 wherein the suspension means suspends processing of a processor when the number of events counted for that processor is not less then the number of events counted for a suspended processor.
Claim 6
Independent Claim
138 words
An apparatus for synchronizing a plurality of processors comprising, for each processor: event indicating means for indicating the occurrence of a prescribed event within the processor; event counting means, connected to the event indicating means, for counting the number of events indicated; comparison means connected for receiving signals from the event counting means for each processor, for providing a signal when the number of events counted for the processor is greater than the number of events counted for another processor; sync request input means for receiving a synchronization request signal; and synchronization means, connected to the sync request input means and to the event counter of suspending processing of the processor in response to a synchronization request signal when the number of events counted for the processor is greater than the number of events counted for another processor.
Claim 7
Independent Claim
138 words
An apparatus for synchronizing a plurality of processors comprising, for each processor: event indicating means for indicating the occurrence of a prescribed event within the processor; event counting means, connected to the event indicating means, for counting the number of events indicated; comparison means connected for receiving signals from the event counting means for each processor, for providing a signal when the number of events counted for the processor is greater than the number of events counted for another processor; sync request input means for receiving a synchronization request signal; and synchronization means, connected to the sync request input means and to the event counter of suspending processing of the processor in response to a synchronization request signal when the number of events counted for the processor is greater than the number of events counted for another processor.
Claim 8
Dependent Claim
35 words
The apparatus according to claim 5 wherein the synchronization means suspends the processor when the number of events counted for the processor is not less than the number of events counted for a suspended processor.
Claim 9
Dependent Claim
28 words
The apparatus according to claim 6 wherein the synchronization means provides a restart signal to the processor when the number of events counted for each processor is equal.
Claim 10
Dependent Claim
33 words
The apparatus according to claim 7 wherein the event counting means further comprises means for providing an sync request signal to the processor when the number of events counted equals a prescribed value.
Claim 11
Dependent Claim
22 words
The apparatus according to claim 8 further comprising a cycle counter for counting a number of clock cycles occurring after an event.
Claim 12
Dependent Claim
35 words
The apparatus according to claim 9 further comprising reset means, connected to the event detecting means and to the cycle counter, for setting the cycle counter to a prescribed value when an event is detected.
Claim 13
Dependent Claim
29 words
The apparatus according to claim 9 further comprising means for providing a sync request signal to the processor when the number of clock cycles counted equals a prescribed value.
Claim 14
Dependent Claim
25 words
The apparatus according to claim 11 further comprising extra clock indicating means for indicating when the processor uses extra clock cycles to execute a program.
Claim 15
Dependent Claim
39 words
The apparatus according to claim 11 wherein the cycle counter further includes disable means, connected to the extra clock indicating means, for inhibiting the counting of clock cycles when the processor uses extra clock cycles to execute a program.
Claim 16
Dependent Claim
148 words
In a multiple processor system wherein each processor executes a program having a plurality of events defined therein, the plurality of events occurring in the same order in each processor, a method of synchronizing each processor with the other processors comprising the steps of, for each processor: indicating the occurrence of a prescribed event; counting the number of events indicated; receiving a synchronization request signal; suspending processing of the processor when the next event is detected; comparing the number of events counted with the number of events counted by the other processors; continuing processing when the number of events counted for the processor is less than the number of events counted for another processor; suspending processing when the number of events counted is equal to the maximum number of events counted by any processor; and continuing processing when the number of events counted for each processor is equal.
Claim 17
Dependent Claim
148 words
In a multiple processor system wherein each processor executes a program having a plurality of events defined therein, the plurality of events occurring in the same order in each processor, a method of synchronizing each processor with the other processors comprising the steps of, for each processor: indicating the occurrence of a prescribed event; counting the number of events indicated; receiving a synchronization request signal; suspending processing of the processor when the next event is detected; comparing the number of events counted with the number of events counted by the other processors; continuing processing when the number of events counted for the processor is less than the number of events counted for another processor; suspending processing when the number of events counted is equal to the maximum number of events counted by any processor; and continuing processing when the number of events counted for each processor is equal.
Claim 18
Dependent Claim
53 words
The method according to claim 14 further comprising the steps of: counting the number of clock cycles occurring after an event is detected; detecting when the number of clock cycles equals a prescribed value; generating an interrupt signal; generating a synchronization request signal; and generating an event in response to the interrupt signal.
Claim 19
Dependent Claim
29 words
The method according to claim 15 further comprising the steps of: detecting the occurrence of extra clock cycles; and inhibiting the clock cycle count during the extra clock cycles.
References Cited (Backward Citations)
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