Process for preferentially etching polycrystalline silicon

Claim 2

A process for etching polycrystalline silicon in preference to and in the presence of exposed monocrystalline silicon comprising the steps of: providing a monocrystalline silicon substrate (10); providing a patterned layer of polycrystalline silicon (14) overlying said substrate (10) and exposing a portion of said substrate; anisotropically etching said patterned layer of polycrystalline silicon (14) in a plasma comprising chlorine and oxygen as reactants without substantially etching said substrate.

Claim 3

The process of claim 1 wherein said chlorine comprises a noncarbonaceous compound of chlorine.

Claim 4

The process of claim 2 wherein said compound comprises Cl₂, ClF₃ or HCl.

Claim 5

The process of claim 1 wherein said plasma further comprises HBr or HI as reactants.

Claim 6

The process of claim 1 wherein said oxygen comprises about 0.4 to about 1.5 percent by volume of said reactants.

Claim 7

A process for fabricating a semiconductor device which comprises the steps of: providing a monocrystalline silicon substrate (30) having a major surface; providing a first layer (34) of insulating material overlying said major surface; depositing a second layer (36) of polycrystalline silicon overlying said first layer (34); patterning said second layer (36) and said first layer (34) to expose a portion (52) of said surface of said monocrystalline silicon substrate (30); anisotropically etching said patterned layer (36) of polycrystalline silicon without substantially etching said surface (52) of said monocrystalline silicon substrate in a plasma comprising a noncarbonaceous silicon etchant and oxygen as reactants.

Claim 8

A process for fabricating a semiconductor device which comprises the steps of: providing a monocrystalline silicon substrate (30) having a major surface; providing a first layer (34) of insulating material overlying said major surface; depositing a second layer (36) of polycrystalline silicon overlying said first layer (34); patterning said second layer (36) and said first layer (34) to expose a portion (52) of said surface of said monocrystalline silicon substrate (30); anisotropically etching said patterned layer (36) of polycrystalline silicon without substantially etching said surface (52) of said monocrystalline silicon substrate in a plasma comprising a noncarbonaceous silicon etchant and oxygen as reactants.

Claim 9

The process of claim 6 wherein said noncarbonaceous silicon etchant comprises a compound selected from the group consisting of Cl₂, SF₆, NF₃, ClF₃, HCl, and combinations thereof.

Claim 10

The process of claim 6 wherein said oxygen comprises about 0.4 to about 1.5 percent by volume of said reactants.

Claim 11

A process for fabricating a semiconductor device which comprises the steps of: providing a monocrystalline silicon substrate (30); forming a gate insulator (34) overlying said substrate; depositing a first layer (36) of polycrystalline silicon overlying said gate insulator (34); forming an interlayer dielectric (38) overlying said first layer (36); patterning said interlayer dielectric (38) and said first layer (36) of polycrystalline silicon; depositing a second layer (44) of polycrystalline silicon overlying said patterned interlayer dielectric (38) and first layer (36) of polycrystalline silicon; patterning said second layer (44) of polycrystalline silicon, said interlayer dielectric (38), and a portion of said gate insulator (34) to thereby expose a portion (52) of said monocrystalline silicon substrate; anisotropically etching said first layer (36) of polycrystalline silicon in self alignment with said second layer (44) of polycrystalline silicon without substantially etching said exposed portion (52) of said monocrystalline silicon substrate (30), said etching comprising subjecting said second layer (44) of polycrystalline silicon to a plasma including a noncarbonaceous silicon etchant and oxygen.

Claim 12

A process for fabricating a semiconductor device which comprises the steps of: providing a monocrystalline silicon substrate (30); forming a gate insulator (34) overlying said substrate; depositing a first layer (36) of polycrystalline silicon overlying said gate insulator (34); forming an interlayer dielectric (38) overlying said first layer (36); patterning said interlayer dielectric (38) and said first layer (36) of polycrystalline silicon; depositing a second layer (44) of polycrystalline silicon overlying said patterned interlayer dielectric (38) and first layer (36) of polycrystalline silicon; patterning said second layer (44) of polycrystalline silicon, said interlayer dielectric (38), and a portion of said gate insulator (34) to thereby expose a portion (52) of said monocrystalline silicon substrate; anisotropically etching said first layer (36) of polycrystalline silicon in self alignment with said second layer (44) of polycrystalline silicon without substantially etching said exposed portion (52) of said monocrystalline silicon substrate (30), said etching comprising subjecting said second layer (44) of polycrystalline silicon to a plasma including a noncarbonaceous silicon etchant and oxygen.

Claim 13

The process of claim 9 wherein said noncarbonaceous silicon etchant is selected from the group consisting of CL₂, HCl, SF₆, NF₃, ClF₃, and combinations thereof.