Electro-optical transducer assembly

Claim 2

An electro-optical transducer assembly comprising: an electro-optical transducer (13, 15) having a pair of serial transmission line terminals, a logic chip (50, 51) including one of serial to parallel or parallel to serial conversion circuitry with both serial terminals and parallel terminals on the same broad surface of said logic chip, and a multi-layer coupling chip (40, 41) mounted between said transducer and said logic chip with one broad surface (40b, 41b) of said coupling chip coupled to said pair of trans­mission line terminals (13b, 13c, 15b, 15c) and with the opposite broad surface (40a, 41a) coupled to said one broad surface of said logic chip at said serial and parallel ter­minals, said coupling chip having feedthrough conductor means for connecting the serial transmission line terminals to the corresponding serial terminals on said logic chip through the thickness of the coupling chip and means for providing a plurality of contacts on one surface of said coupling chip and means coupling said plurality of contacts to said parallel terminals on said logic chip.

Claim 3

An assembly according to claim 1 wherein said plurality of contacts extend along one edge and along a mounting surface of said assembly and including an elastomeric connector mounted along said one edge to provide parallel input or output contacts along the mounting surface of said assembly.

Claim 4

An assembly according to claim 2 including an interposer and wire mesh pads coupled between said transmission line terminals and coupling chip, said interposer including cylind­rical sockets adopted to fit tightly over pin terminals at said transmission line terminals, said wire mesh pads press fitted between said sockets and said coupling chip.

Claim 5

An assembly according to claim 1 including a transducer housing adapted to enclose said transducer except at the ends, said housing having the end nearest the transmission line terminals adapted with a recess to receive and align said coupling chip with respect to said transducer.

Claim 6

An electro-optical transducer assembly comprising: an electro-optical transducer adapted to be coupled to a light transfer medium at one end and a pair of electrical transmission line terminals at the opposite end, an integrated circuit logic chip having broad opposite surfaces with a first plurality of contacts on a first broad surface, said first plurality including a first pair of contacts for providing serial connection to said logic chip and a first set of contacts greater than said pair for pro­viding parallel connection to said logic chip, said logic chip including means for providing serial to parallel or parallel to serial signal translation, and amplifying means, a multi-layer coupling chip having opposite broad sur­faces with a second pair of contacts on one broad surface and a second set of contacts on said opposite broad surface, said second set of contacts including a third pair of contacts and a third set of contacts equal in number and arrangement to match said first set of contacts on said logic chip, said second set of contacts being arranged to match the first set of contacts and first pair of contacts, said multi-layer coupling chip further including a fourth set of contact tabs near one edge of one of said opposite broad surfaces for connection to external conductors, means including coupling layers and vias between said opposite broad surfaces of said multi-layer coupling chip with said second pair of contacts coupled to said third pair of contacts and said third set of contacts coupled to said fourth set of contact tabs, said logic chip being mounted on said coupling chips with said first broad surface on said opposite broad surface of said coupling chip with said first set of contacts and said first pair of contact connected to said third set of contacts and said third pair of contacts respectively, a heat sink adjacent to a broad surface of said logic chip opposite said first surface, and means for coupling said pair of terminals to said second pair of contacts.

Claim 7

An electro-optical transducer assembly comprising: an electro-optical transducer adapted to be coupled to a light transfer medium at one end and a pair of electrical transmission line terminals at the opposite end, an integrated circuit logic chip having broad opposite surfaces with a first plurality of contacts on a first broad surface, said first plurality including a first pair of contacts for providing serial connection to said logic chip and a first set of contacts greater than said pair for pro­viding parallel connection to said logic chip, said logic chip including means for providing serial to parallel or parallel to serial signal translation, and amplifying means, a multi-layer coupling chip having opposite broad sur­faces with a second pair of contacts on one broad surface and a second set of contacts on said opposite broad surface, said second set of contacts including a third pair of contacts and a third set of contacts equal in number and arrangement to match said first set of contacts on said logic chip, said second set of contacts being arranged to match the first set of contacts and first pair of contacts, said multi-layer coupling chip further including a fourth set of contact tabs near one edge of one of said opposite broad surfaces for connection to external conductors, means including coupling layers and vias between said opposite broad surfaces of said multi-layer coupling chip with said second pair of contacts coupled to said third pair of contacts and said third set of contacts coupled to said fourth set of contact tabs, said logic chip being mounted on said coupling chips with said first broad surface on said opposite broad surface of said coupling chip with said first set of contacts and said first pair of contact connected to said third set of contacts and said third pair of contacts respectively, a heat sink adjacent to a broad surface of said logic chip opposite said first surface, and means for coupling said pair of terminals to said second pair of contacts.

Claim 8

An assembly according to claim 5 wherein said fourth set of contacts near said one edge extend along the mounting surface of said assembly and an elastomeric connector is mounted along said one edge to provide parallel output con­tacts along the mounting surface of said assembly.

Claim 9

An assembly according to claim 6 including an interposer and wire mesh pads coupled between said transmission line terminals of said transducer and said second pair of contacts on said multi-layer coupling chip, said interposer including cylindrical sockets that fit tightly over pins at the trans­mission line terminals, said wire mesh pads being press fitted between said sockets and said first pair of contracts on said multi-layer coupling chip.

Claim 10

An assembly according to claim 5 including an interposer and wire mesh pads coupled between said transmission line terminals of said transducer and said second pair of contacts on said multi-layer coupling chip , said interposer including cylindrical sockets that fit tightly over pins at the trans­mission line terminals, said wire mesh pads being press fitted between said sockets and said first pair of contacts on said multi-layer coupling chip.

Claim 11

An electro-optical transducer assembly comprising: a housing for an electro-optical transducer, an electro-optical transducer mounted in said housing for translating between optical data signals and electrical data signals mounted in said housing with transducer connector pins extending at one inboard end,, a heat sink, a logic chip including one of serializing or de-seria­lizing circuitry and amplifiers with serial data contacts and parallel data contacts on a first broad surface of said logic chip, and a multi-layer coupling chip having a first broad surface with a first set of serial data contacts adapted to match with said transducer connector pins and a second broad surface with a second set of serial data contacts and first parallel data contacts with said first set of serial data contacts connected with vias through said chip to said second set of serial data contacts, said multi-layer coupling chip having one of second parallel input or output contacts near one edge with parallel interconnection between said first parallel data contacts and said second parallel contacts, said logic chips mounted with said first broad surface on said second broad surface of said multi-layer chip with said serial data contacts and said parallel data contacts of said logic chip connected on said first set of serial data contacts and said first parallel contacts respectively, said multi-layer coupling chip and logic chip sandwiched between said housing and said heat sink with said transducer connector pins coupled to said first set of serial data contacts and a broad surface of said logic chip opposite said first broad surface in contact with said heat sink.

Claim 12

An electro-optical transducer assembly comprising: a housing for an electro-optical transducer, an electro-optical transducer mounted in said housing for translating between optical data signals and electrical data signals mounted in said housing with transducer connector pins extending at one inboard end,, a heat sink, a logic chip including one of serializing or de-seria­lizing circuitry and amplifiers with serial data contacts and parallel data contacts on a first broad surface of said logic chip, and a multi-layer coupling chip having a first broad surface with a first set of serial data contacts adapted to match with said transducer connector pins and a second broad surface with a second set of serial data contacts and first parallel data contacts with said first set of serial data contacts connected with vias through said chip to said second set of serial data contacts, said multi-layer coupling chip having one of second parallel input or output contacts near one edge with parallel interconnection between said first parallel data contacts and said second parallel contacts, said logic chips mounted with said first broad surface on said second broad surface of said multi-layer chip with said serial data contacts and said parallel data contacts of said logic chip connected on said first set of serial data contacts and said first parallel contacts respectively, said multi-layer coupling chip and logic chip sandwiched between said housing and said heat sink with said transducer connector pins coupled to said first set of serial data contacts and a broad surface of said logic chip opposite said first broad surface in contact with said heat sink.

Claim 13

An assembly according to claim 9 wherein said one of parallel input or output contacts near said one edge extends along one mounting surface of said assembly and an elastomeric connector mounted between said one edge to provide parallel input or output contacts along the mounting surface of said assembly.

Claim 14

An assembly according to claim 9 including an interposer and wire mesh pads coupled between said transducer connector pins and said first set of serial data contacts, said interposer including cylindrical sockets that fit tightly over said pins, said wire mesh pads press being fitted between said sockets and said first set of serial data con­tacts.

Claim 15

An electro-optical transducer assembly comprising: an optical transmitter subassembly and a set of pins at one end and means adapted to couple to optical fibers at the opposite end, a receiver subassembly having means at one end adapted to couple to optical fibers and providing electrical output and a pair of pins at the opposite end, a housing including a pair of apertures spaced from each other and adapted to receive at one of said apertures the transmitter subassembly and the receiver subassembly in the other spaced apart aperture of said subassembly with said pins extending in recesses in the inboard end of said housing, a first logic chip including a serializing circuitry amplifiers and a clock recovery circuit with transmitter serial data contacts and transmitter parallel data contacts on a first broad surface of said first logic chip, a second logic chip including a deserializing circuitry, amplifiers, and clock recovery circuitry with receiver serial data contacts and receiver parallel data contacts on a first broad surface of said second logic chip, a first multi-layer coupling chip having a first broad surface with a first set of transmitter serial data contacts adapted to match with said transmitter set of pins and a second broad surface with a second set of transmitter serial data contacts and first transmitter parallel data contacts with said first set of serial data contacts connected with vias through said chip to said second set of serial data contacts, said first multi-layer coupling chip having parallel input contacts near one edge with parallel interconnects between said first transmitter parallel data contacts and said parallel input contacts, a second multi-layer coupling chip having a first broad surface with a first pair of receiver serial data contacts adapted to match with said receiver pins and a second broad surface with a second pair of receiver serial data contacts and first receiver parallel data contacts with said first pair of receiver serial data contacts connected with vias through said chip to said second pair of receiver serial data con­tacts, said multi-layer coupling chip having parallel output contacts near one edge with parallel interconnects between said first receiver parallel data contacts and said parallel output contacts, said first logic chip mounted with said first broad surface on said second broad surface of said first multi-layer coupling chip with said transmitter serial data contacts and said transmitter parallel data contacts of said logic chip connected on said second set of serial data contacts and said first transmitter parallel data contacts respectively of said first multi-layer coupling chip, said second logic chip mounted with said first broad surface on said second broad surface of said second multi-­layer coupling chip with said receiver serial data contacts and receiver parallel data contacts of said second logic chip connected on said second set of receiver serial data contacts and said first receiver parallel contacts respectively of said second multi-layer coupling chip, said first multi-layer coupling chip and logic chip sandwiched between said housing and said heat sink with transmitter subassembly pins coupled to said first transmitter set of serial data contacts and a broad surface of said logic chip opposite said first broad surface in contact with said heat sink, said second multi-layer coupling chip and said logic chip sandwiched between said housing and said heat sink with said receiver subassembly pins coupled to said first pair of receiver serial data contacts and a broad surface of said logic chip opposite said first broad surface in contact with said heat sink.

Claim 16

An electro-optical transducer assembly comprising: an optical transmitter subassembly and a set of pins at one end and means adapted to couple to optical fibers at the opposite end, a receiver subassembly having means at one end adapted to couple to optical fibers and providing electrical output and a pair of pins at the opposite end, a housing including a pair of apertures spaced from each other and adapted to receive at one of said apertures the transmitter subassembly and the receiver subassembly in the other spaced apart aperture of said subassembly with said pins extending in recesses in the inboard end of said housing, a first logic chip including a serializing circuitry amplifiers and a clock recovery circuit with transmitter serial data contacts and transmitter parallel data contacts on a first broad surface of said first logic chip, a second logic chip including a deserializing circuitry, amplifiers, and clock recovery circuitry with receiver serial data contacts and receiver parallel data contacts on a first broad surface of said second logic chip, a first multi-layer coupling chip having a first broad surface with a first set of transmitter serial data contacts adapted to match with said transmitter set of pins and a second broad surface with a second set of transmitter serial data contacts and first transmitter parallel data contacts with said first set of serial data contacts connected with vias through said chip to said second set of serial data contacts, said first multi-layer coupling chip having parallel input contacts near one edge with parallel interconnects between said first transmitter parallel data contacts and said parallel input contacts, a second multi-layer coupling chip having a first broad surface with a first pair of receiver serial data contacts adapted to match with said receiver pins and a second broad surface with a second pair of receiver serial data contacts and first receiver parallel data contacts with said first pair of receiver serial data contacts connected with vias through said chip to said second pair of receiver serial data con­tacts, said multi-layer coupling chip having parallel output contacts near one edge with parallel interconnects between said first receiver parallel data contacts and said parallel output contacts, said first logic chip mounted with said first broad surface on said second broad surface of said first multi-layer coupling chip with said transmitter serial data contacts and said transmitter parallel data contacts of said logic chip connected on said second set of serial data contacts and said first transmitter parallel data contacts respectively of said first multi-layer coupling chip, said second logic chip mounted with said first broad surface on said second broad surface of said second multi-­layer coupling chip with said receiver serial data contacts and receiver parallel data contacts of said second logic chip connected on said second set of receiver serial data contacts and said first receiver parallel contacts respectively of said second multi-layer coupling chip, said first multi-layer coupling chip and logic chip sandwiched between said housing and said heat sink with transmitter subassembly pins coupled to said first transmitter set of serial data contacts and a broad surface of said logic chip opposite said first broad surface in contact with said heat sink, said second multi-layer coupling chip and said logic chip sandwiched between said housing and said heat sink with said receiver subassembly pins coupled to said first pair of receiver serial data contacts and a broad surface of said logic chip opposite said first broad surface in contact with said heat sink.

Claim 17

An assembly according to claim 12 wherein said parallel input contacts near said one edge extends along one mounting surface of said assembly and an elastomeric connector mounted between said one edge to provide parallel outputs along the mounting surface of said assembly, and wherein said parallel output contact near said one edge extends along one mounting surface of said assembly and a second elastomeric connector mounted between said one edge to provide parallel output contacts along the mounting surface of said assembly.

Claim 18

An assembly according to claim 13 including a first interposer and wire mesh pads coupled between said transmitter subassembly connector pins and said first set of serial data contacts, said first interposing including cylindrical sockets that fit snuggly over said pins, said wire mesh pads being press fitted between said socket and said first set of serial data contacts, and a second interposer and second set of wire mesh pads coupled between said receiver connector pins and said first set of serial data contacts, said second interposer including cy­lindrical sockets that fit snuggly over said pins, said wire mesh pads fitted between said sockets and said first set of serial data contact.